On 06/12/2021 15:29, Mårten Lindahl wrote: > Current dw_mci driver supports a TMOUT register which consists of a 24 > bit field (TMOUT[31:8]) for the DATA_TIMEOUT. The maximum value of this > field is 0xFFFFFF, which with a 200MHz clock will give a full DRTO of: > > 0xFFFFFF / 200000000 => ~84 ms > > However, the ARTPEC-8 SoC DWMMC IP version has a TMOUT register with an > extended DATA_TIMEOUT field, which supports longer timers for the DRTO. > In this version the DATA_TIMEOUT field is split into two, which with the > same 200MHz clock as above will allow a maximum timeout of: > > ((TMOUT[10:8] -1) * 0xFFFFFF + TMOUT[31:11] * 8) / 200000000 => ~587 ms > > Add a quirk to support this. The quirk is enabled for ARTPEC-8 SoCs. > > Signed-off-by: Mårten Lindahl <marten.lindahl@xxxxxxxx> > --- > > v2: > - Removed unnecessary comment > - Change 1<<0 to BIT(0) > > drivers/mmc/host/dw_mmc-exynos.c | 5 +++++ > drivers/mmc/host/dw_mmc.c | 33 ++++++++++++++++++++++++++++---- > drivers/mmc/host/dw_mmc.h | 6 ++++++ > 3 files changed, 40 insertions(+), 4 deletions(-) > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxxxxx> Best regards, Krzysztof
