On 01/12/2021 20:04, Sam Protsenko wrote: > In new Exynos SoCs (like Exynos850) where HSI2C is implemented as a > part of USIv2 block, there are two clocks provided to HSI2C controller: > - PCLK: bus clock (APB), provides access to register interface > - IPCLK: operating IP-core clock; SCL is derived from this one > > Both clocks have to be asserted for HSI2C to be functional in that case. > > Add code to obtain and enable/disable PCLK in addition to already > handled operating clock. Make it optional though, as older Exynos SoC > variants only have one HSI2C clock. > > Signed-off-by: Sam Protsenko <semen.protsenko@xxxxxxxxxx> > --- > drivers/i2c/busses/i2c-exynos5.c | 46 ++++++++++++++++++++++++++------ > 1 file changed, 38 insertions(+), 8 deletions(-) > You could use clk_bulk API, but for two clocks, where one is optional, it won't reduce much of code, so I am fine here: Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxxxxx> Best regards, Krzysztof
