On Wed, Apr 7, 2021 at 2:37 AM Benjamin Gaignard
<benjamin.gaignard@xxxxxxxxxxxxx> wrote:
>
> Introducing the G2 hevc video decoder requires modifications of the bindings to allow
> one node per VPU.
>
> VPUs share one hardware control block which is provided as a phandle on
> a syscon.
> Each node has now one reg and one interrupt.
> Add a compatible for G2 hardware block: nxp,imx8mq-vpu-g2.
>
> To be compatible with older DT the driver is still capable to use the 'ctrl'
> reg-name even if it is deprecated now.
>
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@xxxxxxxxxxxxx>
> Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
> Reviewed-by: Philipp Zabel <p.zabel@xxxxxxxxxxxxxx>
I need to edit the yaml file to add support the imx8mm, but it doesn't
appear that this series has gone anywhere. I know there is still some
waiting on the vpu-blk-ctrl driver, but it seems like the 8mq could
split the codecs out using syscon in place of the blk-ctrl until that
driver is available. If that doesn't work, I might have to introduce
a separate yaml file for mini which could be somehow merged with the
8mq in the future. I am just not sure which way to go right now.
adam
> ---
> version 9:
> - Corrections in commit message
>
> version 7:
> - Add Rob and Philipp reviewed-by tag
> - Change syscon phandle name to nxp,imx8m-vpu-ctrl (remove 'q' to be
> usable for iMX8MM too)
>
> version 5:
> - This version doesn't break the backward compatibilty between kernel
> and DT.
>
> .../bindings/media/nxp,imx8mq-vpu.yaml | 53 ++++++++++++-------
> 1 file changed, 34 insertions(+), 19 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
> index 762be3f96ce9..18e7d40a5f24 100644
> --- a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
> +++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
> @@ -15,22 +15,18 @@ description:
>
> properties:
> compatible:
> - const: nxp,imx8mq-vpu
> + oneOf:
> + - const: nxp,imx8mq-vpu
> + - const: nxp,imx8mq-vpu-g2
>
> reg:
> - maxItems: 3
> -
> - reg-names:
> - items:
> - - const: g1
> - - const: g2
> - - const: ctrl
> + maxItems: 1
>
> interrupts:
> - maxItems: 2
> + maxItems: 1
>
> interrupt-names:
> - items:
> + oneOf:
> - const: g1
> - const: g2
>
> @@ -46,14 +42,18 @@ properties:
> power-domains:
> maxItems: 1
>
> + nxp,imx8m-vpu-ctrl:
> + description: Specifies a phandle to syscon VPU hardware control block
> + $ref: "/schemas/types.yaml#/definitions/phandle"
> +
> required:
> - compatible
> - reg
> - - reg-names
> - interrupts
> - interrupt-names
> - clocks
> - clock-names
> + - nxp,imx8m-vpu-ctrl
>
> additionalProperties: false
>
> @@ -62,18 +62,33 @@ examples:
> #include <dt-bindings/clock/imx8mq-clock.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
>
> - vpu: video-codec@38300000 {
> + vpu_ctrl: syscon@38320000 {
> + compatible = "nxp,imx8mq-vpu-ctrl", "syscon";
> + reg = <0x38320000 0x10000>;
> + };
> +
> + vpu_g1: video-codec@38300000 {
> compatible = "nxp,imx8mq-vpu";
> - reg = <0x38300000 0x10000>,
> - <0x38310000 0x10000>,
> - <0x38320000 0x10000>;
> - reg-names = "g1", "g2", "ctrl";
> - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "g1", "g2";
> + reg = <0x38300000 0x10000>;
> + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "g1";
> + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> + <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
> + <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> + clock-names = "g1", "g2", "bus";
> + power-domains = <&pgc_vpu>;
> + nxp,imx8m-vpu-ctrl = <&vpu_ctrl>;
> + };
> +
> + vpu_g2: video-codec@38310000 {
> + compatible = "nxp,imx8mq-vpu-g2";
> + reg = <0x38300000 0x10000>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "g2";
> clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
> <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> clock-names = "g1", "g2", "bus";
> power-domains = <&pgc_vpu>;
> + nxp,imx8m-vpu-ctrl = <&vpu_ctrl>;
> };
> --
> 2.25.1
>
>
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