Hi Shimoda-san,
On Mon, Nov 29, 2021 at 9:36 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@xxxxxxxxxxx> wrote:
> > From: Geert Uytterhoeven, Sent: Wednesday, November 24, 2021 10:48 PM
> > On Tue, Nov 16, 2021 at 8:42 AM Yoshihiro Shimoda
> > <yoshihiro.shimoda.uh@xxxxxxxxxxx> wrote:
> > > Initial support for R-Car S4-8 (r8a779f0), including core, module
> > > clocks, resets, and register access, because register specification
> > > differs from R-Car Gen2/3. The register layout of V3U is a similar
> > > with R-Car S4-8 so that renames CLK_REG_LAYOUT_RCAR_V3U as
> > > CLK_REG_LAYOUT_RCAR_GEN4. However, PLL names differ between V3U
> > > and S4-8.
> > >
> > > Inspired by patches in the BSP by LUU HOAI.
> > >
> > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
> > > +
> > > + DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
> > > + DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1),
> > > + DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1),
> > > + DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1),
> > > + DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1),
> > > + DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 2, 1),
> > > + DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
> > > + DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL5_DIV2, 2, 1),
> >
> > This relies on the default setting of the SD-IF0 Clock Frequency
> > Control Register 1 (SD0CKCR1)?
>
> You're correct. So, we should not use DEF_FIXED for SDSRC...
You can use DEF_FIXED in the initial version, and add proper SD0CKCR1
support later.
This is similar to the handling of the various PLLs: currently they're
treated as fixed ratio clocks, later they can become programmable by
adding support for the PLLnCR1 registers.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
