Hi Romain,
On Sat, 27 Nov 2021 at 05:22, Romain Perier <romain.perier@xxxxxxxxx> wrote:
>
> This defines the real oscillators as input of timer1 and timer2 and
> switch to "mstar,ssd20xd-timer".
>
> Signed-off-by: Romain Perier <romain.perier@xxxxxxxxx>
> ---
> .../arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi b/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi
> index 6f067da61ba3..6ff1f02e00a0 100644
> --- a/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi
> +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi
> @@ -6,6 +6,14 @@
>
> #include "mstar-infinity2m.dtsi"
>
> +/ {
> + xtal_timer: timer_xtal {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <432000000>;
> + };
> +};
mm I think xtal is a bit confusing here. This isn't an external
crystal but a fixed clock because we can't find where the clock is
coming from yet.
So maybe this should be s/xtal/clk/ or something?
Maybe a comment about why we need this like "A header in the vendor
kernel says the timers clk comes from XIU clock but we don't know
what/where XIU clock is yet".
> &gpio {
> compatible = "sstar,ssd20xd-gpio";
> status = "okay";
> @@ -15,3 +23,13 @@ &smpctrl {
> compatible = "sstar,ssd201-smpctrl", "mstar,smpctrl";
> status = "okay";
> };
> +
> +&timer1 {
> + compatible = "mstar,ssd20xd-timer";
> + clocks = <&xtal_timer>;
> +};
I think we should do this for timer0 too. As the below hunk in the
driver will change the clock divider (For others reading this: The
boot ROM in the chip sets a divider for timer0 to get something ~12MHz
to stay compatible with their u-boot that expects 12MHz)) and timer0
will have the right clock rate instead of the roughly 12MHz but not
really 12MHz frequency it has from boot and we don't need to rely on
the divider value for timer0 being correct on boot.
+ if (of_device_is_compatible(np, "mstar,ssd20xd-timer")) {
+ to->of_clk.rate = clk_get_rate(to->of_clk.clk) /
MSC313E_CLK_DIVIDER;
+ to->of_clk.period = DIV_ROUND_UP(to->of_clk.rate, HZ);
+ writew(MSC313E_CLK_DIVIDER - 1, timer_of_base(to) +
MSC313E_REG_TIMER_DIVIDE);
+ }
+
Cheers,
Daniel
