On 2021-11-19 04:41, Rob Herring wrote:
On Thu, Nov 18, 2021 at 07:44:51PM +0530, Anilkumar Kolli wrote:
Ath11k driver supports PCI devices such as QCN9074/QCA6390.
Ath11k firmware uses host DDR memory, DT entry is used to reserve
these host DDR memory regions, send these memory base
addresses using DT entries.
Signed-off-by: Anilkumar Kolli <akolli@xxxxxxxxxxxxxx>
---
V2:
- Use reserved-memory (Rob)
.../bindings/net/wireless/qcom,ath11k.yaml | 48
++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git
a/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml
b/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml
index 85c2f699d602..5a8994f6cb10 100644
--- a/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml
+++ b/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml
@@ -150,6 +150,12 @@ properties:
string to uniquely identify variant of the calibration data in
the
board-2.bin for designs with colliding bus and device specific
ids
+ memory-region:
+ maxItems: 1
+ description:
+ phandle to a node describing reserved memory (System RAM
memory)
+ used by ath11k firmware (see
bindings/reserved-memory/reserved-memory.txt)
+
required:
- compatible
- reg
@@ -279,3 +285,45 @@ examples:
"tcl2host-status-ring";
qcom,rproc = <&q6v5_wcss>;
};
+
This looks like a separate example. Please split to its own entry.
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0x0 0x20000000>;
+ };
Outside the scope of what's needed in the example.
Yes, memory entry is available in
"arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi"
Since its used in ath11k patch, added example.
I will remove in next version.
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ qcn9074_pcie0: qcn9074_pcie0@51100000 {
+ no-map;
+ reg = <0x0 0x51100000 0x0 0x03500000>;
+ };
+
+ qcn9074_pcie1: qcn9074_pcie1@54600000 {
+ no-map;
+ reg = <0x0 0x54600000 0x0 0x03500000>;
+ };
+ };
As is this really.
ipq8074-hk10.dtsi board supports two PCI bus and QCN9074 on each PCI.
So added two separate entries to reserves memory for each QCN9074.
+
+ pcie0_rp: pcie0_rp {
+ reg = <0 0 0 0 0>;
This isn't a valid PCI bus binding.
Got it, let me rework in next patch.
+
+ status = "ok";
Don't need status.
Sure, will remove in next patch.
+ ath11k_0: ath11k@0 {
wifi@0
+ reg = <0 0 0 0 0 >;
+ memory-region = <&qcn9074_pcie0>;
+ };
+ };
+
+ pcie1_rp: pcie1_rp {
+ reg = <0 0 0 0 0>;
+
+ status = "ok";
+ ath11k_1: ath11k@1 {
+ reg = <0 0 0 0 0 >;
unit-address and reg don't match.
will update in next patch.
Why do we need 2 nodes in the first place?
ipq8074-hk10.dtsi board supports two PCI bus and QCN9074 on each PCI.
So added two separate entries to reserves memory for each QCN9074.
Since its example, Shall I remove one ?
+ memory-region = <&qcn9074_pcie1>;
+ };
+ };
+
--
2.7.4
- Anil.
