On Tue, 02 Nov 2021 17:11:17 +0100, Emil Renner Berthing wrote: > Add bindings for the reset controller on the JH7100 RISC-V SoC by > StarFive Ltd. This is a test chip for their upcoming JH7110 SoC. > > Signed-off-by: Emil Renner Berthing <kernel@xxxxxxxx> > --- > .../bindings/reset/starfive,jh7100-reset.yaml | 38 +++++++++++++++++++ > 1 file changed, 38 insertions(+) > create mode 100644 Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml > Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
