From: Peng Fan <peng.fan@xxxxxxx>
i.MX8QXP A35 Cluster has 32KB Icache, 32KB Dcache and 512KB L2 Cache
- Icache is 2-way set associative
- Dcache is 4-way set associative
- L2cache is 8-way set associative
- Line size are 64bytes
Signed-off-by: Peng Fan <peng.fan@xxxxxxx>
---
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 28 ++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 617618edf77e..dbec7c106e0b 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -58,6 +58,12 @@ A35_0: cpu@0 {
compatible = "arm,cortex-a35";
reg = <0x0 0x0>;
enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&A35_L2>;
clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
operating-points-v2 = <&a35_opp_table>;
@@ -69,6 +75,12 @@ A35_1: cpu@1 {
compatible = "arm,cortex-a35";
reg = <0x0 0x1>;
enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&A35_L2>;
clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
operating-points-v2 = <&a35_opp_table>;
@@ -80,6 +92,12 @@ A35_2: cpu@2 {
compatible = "arm,cortex-a35";
reg = <0x0 0x2>;
enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&A35_L2>;
clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
operating-points-v2 = <&a35_opp_table>;
@@ -91,6 +109,12 @@ A35_3: cpu@3 {
compatible = "arm,cortex-a35";
reg = <0x0 0x3>;
enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&A35_L2>;
clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
operating-points-v2 = <&a35_opp_table>;
@@ -99,6 +123,10 @@ A35_3: cpu@3 {
A35_L2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
+ cache-size = <0x80000>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
};
};
--
2.25.1
