Add IRQC node to R9A07G044 (RZ/G2L) SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 60 ++++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 358db254c4ea..c42ff2ed3144 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -504,6 +504,10 @@
reg = <0 0x11030000 0 0x10000>;
gpio-controller;
#gpio-cells = <2>;
+ #address-cells = <2>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&irqc>;
+ interrupt-controller;
gpio-ranges = <&pinctrl 0 0 392>;
clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
power-domains = <&cpg>;
@@ -512,6 +516,62 @@
<&cpg R9A07G044_GPIO_SPARE_RESETN>;
};
+ irqc: interrupt-controller@110a0000 {
+ compatible = "renesas,r9a07g044-irqc",
+ "renesas,rzg2l-irqc";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0x110a0000 0 0x10000>;
+ interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <9 0 &gic GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
+ <10 0 &gic GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
+ <11 0 &gic GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
+ <12 0 &gic GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
+ <13 0 &gic GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
+ <14 0 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
+ <15 0 &gic GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
+ <16 0 &gic GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
+ <17 0 &gic GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
+ <18 0 &gic GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
+ <19 0 &gic GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
+ <20 0 &gic GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
+ <21 0 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
+ <22 0 &gic GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
+ <23 0 &gic GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
+ <24 0 &gic GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
+ <25 0 &gic GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
+ <26 0 &gic GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
+ <27 0 &gic GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
+ <28 0 &gic GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
+ <29 0 &gic GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
+ <30 0 &gic GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
+ <31 0 &gic GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
+ <32 0 &gic GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
+ <33 0 &gic GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
+ <34 0 &gic GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
+ <35 0 &gic GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
+ <36 0 &gic GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
+ <37 0 &gic GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
+ <38 0 &gic GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
+ <39 0 &gic GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
+ <40 0 &gic GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <40 0>;
+ clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
+ <&cpg CPG_MOD R9A07G044_IA55_PCLK>;
+ clock-names = "clk", "pclk";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_IA55_RESETN>;
+ };
+
dmac: dma-controller@11820000 {
compatible = "renesas,r9a07g044-dmac",
"renesas,rz-dmac";
--
2.17.1
