This patch series aims to add WDT driver support for RZ/G2L SoC's.
WDT has 3 channels
1) CH0 to check the operation of Cortex-A55-CPU Core0
2) CH1 to check the operation of Cortex-A55-CPU Core1
3) CH2 to check the operation of Cortex-M33 CPU
WDT IP supports
1) Normal Watchdog Timer Function
2) Reset Request Function due to CPU Parity Error
Once the software activates the watchdog timer, the watchdog timer does
not stop until it is reset.
The WDT Overflow System Reset Register (CPG_WDTOVF_RST) and
WDT Reset Selector Register (CPG_WDTRST_SEL) are in CPG IP
block.
Current driver support is basic normal Watchdog Timer Function.
Later will extend support to identify the WDT channel that generated
the reset request using CPG_WDTOVF_RST. Need to figure out how to expose
this to WDT driver from CPG driver?
and also Reset Request Function due to CPU Parity Error.
Tested WDT driver with selftests tool and reboot command
All 3 channels tested with below command.
cat /dev/watchdog & for i in {1..60}; do sleep 1; echo $i; devmem2 0x12800808; done
cat /dev/watchdog1 & for i in {1..60}; do sleep 1; echo $i; devmem2 0x12800c08; done
cat /dev/watchdog2 & for i in {1..60}; do sleep 1; echo $i; devmem2 0x12800408; done
Please share your valuable comments.
Biju Das (4):
clk: renesas: rzg2l: Add support for watchdog reset selection
dt-bindings: watchdog: renesas,wdt: Add support for RZ/G2L
clk: renesas: r9a07g044: Add WDT clock and reset entries
watchdog: Add Watchdog Timer driver for RZ/G2L
.../bindings/watchdog/renesas,wdt.yaml | 72 +++--
drivers/clk/renesas/r9a07g044-cpg.c | 37 +++
drivers/clk/renesas/rzg2l-cpg.c | 6 +
drivers/clk/renesas/rzg2l-cpg.h | 14 +
drivers/watchdog/Kconfig | 8 +
drivers/watchdog/Makefile | 1 +
drivers/watchdog/rzg2l_wdt.c | 281 ++++++++++++++++++
7 files changed, 401 insertions(+), 18 deletions(-)
create mode 100644 drivers/watchdog/rzg2l_wdt.c
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2.17.1
