Hi Stephen,
On Sun, Oct 17, 2021 at 8:51 AM Sergio Paracuellos
<sergio.paracuellos@xxxxxxxxx> wrote:
>
> Hi Stephen,
>
> On Wed, Oct 6, 2021 at 1:23 PM Sergio Paracuellos
> <sergio.paracuellos@xxxxxxxxx> wrote:
> >
> > Hi all,
> >
> > This patch series add minimal change to provide mt7621 resets properly
> > defining them in the 'mediatek,mt7621-sysc' node which is the system
> > controller of the SoC and is already providing clocks to the rest of
> > the world.
> >
> > There is shared architecture code for all ralink platforms in 'reset.c'
> > file located in 'arch/mips/ralink' but the correct thing to do to align
> > hardware with software seems to define and add related reset code to the
> > already mainlined clock driver.
> >
> > After this changes, we can get rid of the useless reset controller node
> > in the device tree and use system controller node instead where the property
> > '#reset-cells' has been added. Binding documentation for this nodeq has
> > been updated with the new property accordly.
> >
> > This series also provide a bindings include header where all related
> > reset bits for the MT7621 SoC are defined.
> >
> > Also, please take a look to this review [0] to understand better motivation
> > for this series.
> >
> > Thanks in advance for your feedback.
> >
> > Changes in v2:
> > - Address review comments of Dan Carpenter [1]:
> > + Avoid 'inline' in function definition.
> > + Return proper error codes (-EINVAL) instead of '-1'.
> > + Make use of 'devm_kzalloc' instead of 'kzalloc'.
>
> Can you please take a look into this series? I'd like them to be added
> in the next merge window and if something needs to be changed I'd like
> to have a bit of time to do it :)).
>
> Regarding how to merge this I guess all of the patches should apply
> cleanly in any tree but since there are already changes in mt7621-dts
> maybe patches 1 and 4 which are related can go through the staging
> tree (if Greg is ok with this) and the bindings doc change and driver
> changes (patches 2 and 3) can go through your tree.
I have just sent v3 since PATCH 4 did not apply cleanly anymore in
both clock tree and staging tree.
Best regards,
Sergio Paracuellos
>
> Thanks in advance for your time.
>
> Best regards,
> Sergio Paracuellos
>
> >
> > Best regards,
> > Sergio Paracuellos
> >
> > [0]: https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20210926145931.14603-3-sergio.paracuellos@xxxxxxxxx/
> > [1]: https://lkml.org/lkml/2021/10/6/204
> >
> > Sergio Paracuellos (4):
> > dt-bindings: reset: add dt binding header for Mediatek MT7621 resets
> > dt-bindings: clock: mediatek,mt7621-sysc: add '#reset-cells' property
> > clk: ralink: make system controller node a reset provider
> > staging: mt7621-dts: align resets with binding documentation
> >
> > .../bindings/clock/mediatek,mt7621-sysc.yaml | 12 +++
> > drivers/clk/ralink/clk-mt7621.c | 79 +++++++++++++++++++
> > drivers/staging/mt7621-dts/mt7621.dtsi | 27 +++----
> > include/dt-bindings/reset/mt7621-reset.h | 37 +++++++++
> > 4 files changed, 140 insertions(+), 15 deletions(-)
> > create mode 100644 include/dt-bindings/reset/mt7621-reset.h
> >
> > --
> > 2.33.0
> >
