On 20 Oct 2021, at 12:27, Anup Patel <anup@xxxxxxxxxxxxxx> wrote: > > On Wed, Oct 20, 2021 at 3:06 PM Heinrich Schuchardt > <heinrich.schuchardt@xxxxxxxxxxxxx> wrote: >> >> The CLINT in the T-HEAD 9xx CPUs is similar to the SiFive CLINT but does >> not support 64bit mmio access to the MTIMER device. >> >> OpenSBI currently uses a property 'clint,has-no-64bit-mmio' to indicate the >> restriction and the "sifive,cling0" compatible string. An OpenSBI >> patch suggested to use "reg-io-width = <4>;" as the reg-io-width property >> is generally used in the devicetree schema for such a condition. >> >> As the design is not SiFive based it is preferable to apply a compatible >> string identifying T-HEAD instead. >> >> Add a new yaml file describing the T-HEAD CLINT. >> >> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@xxxxxxxxxxxxx> >> --- >> @Palmer, @Anup >> I copied you as maintainers from sifive,clint.yaml. Please, indicate if >> this should be changed. >> >> For the prior discussion see: >> https://lore.kernel.org/all/20211015100941.17621-1-heinrich.schuchardt@xxxxxxxxxxxxx/ >> https://lore.kernel.org/all/20211015120735.27972-1-heinrich.schuchardt@xxxxxxxxxxxxx/ >> >> A release candidate of the ACLINT specification is available at >> https://github.com/riscv/riscv-aclint/releases > > T-HEAD supporting only 32bit accesses to MTIME and MTIMECMP > registers are totally allowed. The RISC-V privileged specification does > not enforce RV64 platforms to support 64bit accesses to MTIME and > MTIMECMP registers It does. See [1]. Jess [1] https://github.com/riscv/riscv-isa-manual/commit/50694a2c0d5393690a9e0c8d309cf064f6c8c0e4
