On Sat 16 Oct 11:36 CDT 2021, Dmitry Baryshkov wrote:
> On Sat, 16 Oct 2021 at 01:11, Bjorn Andersson
> <bjorn.andersson@xxxxxxxxxx> wrote:
[..]
> > diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c
[..]
> > +#define QSERDES_COM_SSC_EN_CENTER 0x0010
> > +#define QSERDES_COM_SSC_ADJ_PER1 0x0014
> > +#define QSERDES_COM_SSC_PER1 0x001c
> > +#define QSERDES_COM_SSC_PER2 0x0020
> > +#define QSERDES_COM_SSC_STEP_SIZE1_MODE0 0x0024
> > +#define QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x0028
>
> I think we might want to use register definitions from phy-qcom-qmp.h,
> so that it would be obvious, which generations are handled by the
> driver.
>
I reviewed the all the registers and concluded that the QSERDES is V4,
so I included phy-qcom-qmp.h and used the SERDES_V4 defines instead.
The registers found in the PHY and LANE_TX blocks are specific to this
PHY, so I'm keeping these here.
[..]
> > +/*
> > + * Display Port PLL driver block diagram for branch clocks
>
> Embedded DisplayPort
>
Sounds good, I also updated the drawing below where suitable.
> > + *
> > + * +------------------------------+
> > + * | DP_VCO_CLK |
> > + * | |
> > + * | +-------------------+ |
> > + * | | (DP PLL/VCO) | |
> > + * | +---------+---------+ |
> > + * | v |
> > + * | +----------+-----------+ |
[..]
> > +static struct clk_hw *
> > +qcom_edp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
> > +{
> > + unsigned int idx = clkspec->args[0];
> > + struct qcom_edp *edp = data;
> > +
> > + if (idx >= 2) {
> > + pr_err("%s: invalid index %u\n", __func__, idx);
> > + return ERR_PTR(-EINVAL);
> > + }
> > +
> > + if (idx == 0)
> > + return &edp->dp_link_hw;
> > +
> > + return &edp->dp_pixel_hw;
> > +}
>
> You might want to use of_clk_hw_onecell_get() instead of the special function.
>
Yeah, that looks slightly cleaner.
> > +
> > +static int qcom_edp_clks_register(struct qcom_edp *edp, struct device_node *np)
> > +{
> > + struct clk_init_data init = { };
> > + int ret;
> > +
> > + init.ops = &qcom_edp_dp_link_clk_ops;
> > + init.name = "edp_phy_pll_link_clk";
> > + edp->dp_link_hw.init = &init;
> > + ret = devm_clk_hw_register(edp->dev, &edp->dp_link_hw);
> > + if (ret)
> > + return ret;
> > +
> > + init.ops = &qcom_edp_dp_pixel_clk_ops;
> > + init.name = "edp_phy_pll_vco_div_clk";
> > + edp->dp_pixel_hw.init = &init;
> > + ret = devm_clk_hw_register(edp->dev, &edp->dp_pixel_hw);
> > + if (ret)
> > + return ret;
> > +
> > + return devm_of_clk_add_hw_provider(edp->dev, qcom_edp_dp_clks_hw_get, edp);
> > +}
[..]
> > +static struct platform_driver qcom_edp_phy_driver = {
> > + .probe = qcom_edp_phy_probe,
> > + .driver = {
> > + .name = "qcom-edp-phy",
> > + .of_match_table = qcom_edp_phy_match_table,
> > + },
> > +};
> > +
> > +module_platform_driver(qcom_edp_phy_driver);
> > +
> > +MODULE_DESCRIPTION("Qualcomm eDP PHY driver");
>
> Should we mention that it's a eDP QMP PHY driver in contrast to the
> old eDP from 8x74/8x84?
>
Sure.
> Also MODULE_AUTHOR seems to be missing.
>
Okay, I can add one of those.
Thanks,
Bjorn
> > +MODULE_LICENSE("GPL v2");
> > --
> > 2.29.2
> >
>
>
> --
> With best wishes
> Dmitry
