Hi Samuel, On 10/4/21 10:27 AM, Samuel Holland wrote: > This driver works by adjusting the divider on the DRAM controller's > module clock. Thus there is no fixed set of OPPs, only "full speed" down > to "quarter speed" (or whatever the maximum divider is on that variant). > > It makes use of the MDFS hardware in the MBUS, in "DFS" mode, which > takes care of updating registers during the critical section while DRAM > is inaccessible. > > This driver should support several sunxi SoCs, starting with the A33, > which have a DesignWare DDR3 controller with merged PHY register space > and the matching MBUS register layout (so not A63 or later). However, > the driver has only been tested on the A64/H5, so those are the only > compatibles enabled for now. > > Signed-off-by: Samuel Holland <samuel@xxxxxxxxxxxx> > --- > drivers/devfreq/Kconfig | 8 + > drivers/devfreq/Makefile | 1 + > drivers/devfreq/sun8i-a33-mbus.c | 511 +++++++++++++++++++++++++++++++ > 3 files changed, 520 insertions(+) > create mode 100644 drivers/devfreq/sun8i-a33-mbus.c (snip) Looks good to me. Acked-by: Chanwoo Choi <cw00.choi@xxxxxxxxxxx> -- Best Regards, Chanwoo Choi Samsung Electronics
