On Wed, Oct 13, 2021 at 9:52 PM Adam Ford <aford173@xxxxxxxxx> wrote:
>
> There is a csi bridge and csis interface that tie together
> to allow csi2 capture.
>
> Signed-off-by: Adam Ford <aford173@xxxxxxxxx>
Laurent,
Since you did some work to make the csis functional on the imx8mm, I
was hoping you might have some insights. Please see below:
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index c2f3f118f82e..8a8a5d0a4a1e 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -1068,6 +1068,22 @@ aips4: bus@32c00000 {
> #size-cells = <1>;
> ranges = <0x32c00000 0x32c00000 0x400000>;
>
> + csi: csi@32e20000 {
> + compatible = "fsl,imx7-csi";
> + reg = <0x32e20000 0x1000>;
> + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_CSI1_ROOT>;
> + clock-names = "mclk";
> + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_CSI_BRIDGE>;
> + status = "disabled";
> +
> + port {
> + csi_in: endpoint {
> + remote-endpoint = <&imx8mm_mipi_csi_out>;
> + };
> + };
> + };
> +
> disp_blk_ctrl: blk-ctrl@32e28000 {
> compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
> reg = <0x32e28000 0x100>;
> @@ -1095,6 +1111,41 @@ disp_blk_ctrl: blk-ctrl@32e28000 {
> #power-domain-cells = <1>;
> };
>
> + mipi_csi2: mipi-csi@32e30000 {
> + compatible = "fsl,imx8mm-mipi-csi2";
> + reg = <0x32e30000 0x1000>;
> + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <333000000>;
> + clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
> + <&clk IMX8MM_CLK_CSI1_ROOT>,
> + <&clk IMX8MM_CLK_CSI1_PHY_REF>,
> + <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
When comparing clock parents and the clock rates to one of NXP's
kernels, it appears we need assigned-clocks and assigned-clock-parents
to allow the CSI1 clocks to run fast enough.
assigned-clocks = <&clk IMX8MM_CLK_CSI1_PHY_REF>,
<&clk IMX8MM_CLK_CSI1_CORE>,
<&clk IMX8MM_CLK_CSI1_ROOT>,
<&clk IMX8MM_CLK_CSI1_ESC>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
<&clk IMX8MM_SYS_PLL2_1000M>,
<&clk IMX8MM_CLK_CSI1_CORE>,
<&clk IMX8MM_SYS_PLL1_800M>;
However, even with this, I am attempting to capture. While I can get
the pipeline enabled, when I try to capture a file, I get no data. i
can use control-c to exit gstreamer, so I know the kernel didn't hang.
I don't get errors, but I don't get data either.
Any ideas if what/if any other clock entries might be missing?
> + clock-names = "pclk", "wrap", "phy", "axi";
> + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_CSI>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + imx8mm_mipi_csi_in: endpoint {
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + imx8mm_mipi_csi_out: endpoint {
> + remote-endpoint = <&csi_in>;
> + };
> + };
> + };
> + };
> +
> +
> usbotg1: usb@32e40000 {
> compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
> reg = <0x32e40000 0x200>;
> --
> 2.25.1
>
