Le lundi 19 juillet 2021 à 17:52 -0300, Ezequiel Garcia a écrit :
> Given H.264 support for VDPU2 was just added, let's enable it.
> For now, this is only enabled on platform that don't have
> an RKVDEC core, such as RK3328.
There is a small oops, the decoder is now visible on RK3399. At least for
GStreamer, it got tricked in picking it by default, which regress decoding
performance. I still think we should wait before enabling it until we know that
userspace have infrastructure to rank them properly.
>
> Signed-off-by: Ezequiel Garcia <ezequiel@xxxxxxxxxxxxx>
> Tested-by: Alex Bee <knaerzche@xxxxxxxxx>
> ---
> .../staging/media/hantro/rockchip_vpu_hw.c | 26 ++++++++++++++++++-
> 1 file changed, 25 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c
> index 3ccc16413f42..e4e3b5e7689b 100644
> --- a/drivers/staging/media/hantro/rockchip_vpu_hw.c
> +++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c
> @@ -162,6 +162,19 @@ static const struct hantro_fmt rk3399_vpu_dec_fmts[] = {
> .fourcc = V4L2_PIX_FMT_NV12,
> .codec_mode = HANTRO_MODE_NONE,
> },
> + {
> + .fourcc = V4L2_PIX_FMT_H264_SLICE,
> + .codec_mode = HANTRO_MODE_H264_DEC,
> + .max_depth = 2,
> + .frmsize = {
> + .min_width = 48,
> + .max_width = 1920,
> + .step_width = MB_DIM,
> + .min_height = 48,
> + .max_height = 1088,
> + .step_height = MB_DIM,
> + },
> + },
> {
> .fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
> .codec_mode = HANTRO_MODE_MPEG2_DEC,
> @@ -388,6 +401,12 @@ static const struct hantro_codec_ops rk3399_vpu_codec_ops[] = {
> .init = hantro_jpeg_enc_init,
> .exit = hantro_jpeg_enc_exit,
> },
> + [HANTRO_MODE_H264_DEC] = {
> + .run = rockchip_vpu2_h264_dec_run,
> + .reset = rockchip_vpu2_dec_reset,
> + .init = hantro_h264_dec_init,
> + .exit = hantro_h264_dec_exit,
> + },
> [HANTRO_MODE_MPEG2_DEC] = {
> .run = rockchip_vpu2_mpeg2_dec_run,
> .reset = rockchip_vpu2_dec_reset,
> @@ -433,6 +452,8 @@ static const char * const rockchip_vpu_clk_names[] = {
> "aclk", "hclk"
> };
>
> +/* VDPU1/VEPU1 */
> +
> const struct hantro_variant rk3036_vpu_variant = {
> .dec_offset = 0x400,
> .dec_fmts = rk3066_vpu_dec_fmts,
> @@ -495,11 +516,14 @@ const struct hantro_variant rk3288_vpu_variant = {
> .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
> };
>
> +/* VDPU2/VEPU2 */
> +
> const struct hantro_variant rk3328_vpu_variant = {
> .dec_offset = 0x400,
> .dec_fmts = rk3399_vpu_dec_fmts,
> .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
> - .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER,
> + .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
> + HANTRO_H264_DECODER,
> .codec_ops = rk3399_vpu_codec_ops,
> .irqs = rockchip_vdpu2_irqs,
> .num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs),
