Re: [PATCH 2/2] media: adv7604: Add ability to read default input port from DT

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On Wed, Aug 13, 2014 at 01:14:35PM +0100, Ian Molton wrote:
> On Mon, 11 Aug 2014 13:19:02 +0100
> Mark Rutland <mark.rutland@xxxxxxx> wrote:
> 
> > > -  - pclk-sample: Pixel clock polarity. Defaults to output on the falling edge.
> > > +  - pclk-sample:  Pixel clock polarity. Defaults to output on the falling edge.
> > 
> > Unrelated whitespace change?
> 
> Is there a sensible way to get miniscule whitespace changes in?

Just mention it in the commit message.

> > >    If none of hsync-active, vsync-active and pclk-sample is specified the
> > >    endpoint will use embedded BT.656 synchronization.
> > >  
> > > +  - default-input: Select which input is selected after reset.
> > 
> > Valid values are?
> 
> Chip dependent. 0 for 7611, 0-1 for 7612, I expect there are other chips in the family with differing numbers of inputs.

Ok. Can this be mentioned in the documentation?

Cheers,
Mark.

> > > +	 if (!of_property_read_u32(endpoint, "default_input", &v))
> > 
> > This doesn't match the binding ('_' vs '-').
> 
> Good catch!
> 
> -- 
> Ian Molton <ian.molton@xxxxxxxxxxxxxxx>
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