DP_INTF is a similar functional block to mediatek,dpi but is different
in that it serves the DisplayPort controller on mediatek SoCs and uses
different clocks. Therefore this patch creates a new binding file for
this functional block.
Signed-off-by: Markus Schneider-Pargmann <msp@xxxxxxxxxxxx>
---
Notes:
Changes v3 -> v4:
- Fixed clock names in the example as the clock patch series is merged into
next now
- Add missing ports decleration to the example
Changes v1 -> v2:
- Move the devicetree binding from mediatek,dpi into its own binding file.
.../display/mediatek/mediatek,dpintf.yaml | 86 +++++++++++++++++++
1 file changed, 86 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dpintf.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpintf.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpintf.yaml
new file mode 100644
index 000000000000..3b5e0c148c97
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpintf.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,dpintf.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek DP_INTF Controller Device Tree Bindings
+
+maintainers:
+ - CK Hu <ck.hu@xxxxxxxxxxxx>
+ - Jitao shi <jitao.shi@xxxxxxxxxxxx>
+
+description: |
+ The Mediatek DP_INTF function block is a sink of the display subsystem
+ connected to the display port controller.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8195-dpintf
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: hf_fmm Clock
+ - description: hf_fdp Clock
+ - description: Pixel Clock
+ - description: DP_INTF PLL
+
+ clock-names:
+ items:
+ - const: hf_fmm
+ - const: hf_fdp
+ - const: pixel
+ - const: pll
+
+ port:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Output port node. This port should be connected to the input port of an
+ attached display port controller.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/clock/mt8195-clk.h>
+
+ dp_intf1: dp_intf1@1c113000 {
+ compatible = "mediatek,mt8195-dpintf";
+ reg = <0 0x1c113000 0 0x1000>;
+ interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
+ <&vdosys1 CLK_VDO1_DPINTF>,
+ <&topckgen CLK_TOP_DP>,
+ <&topckgen CLK_APMIXED_TVDPLL2>;
+ clock-names = "hf_fmm",
+ "hf_fdp",
+ "pixel",
+ "pll";
+
+ ports {
+ port {
+ dpintf1_out: endpoint {
+ remote-endpoint = <&dp_in>;
+ };
+ };
+ };
+ };
+
+...
--
2.33.0
