On 10/10/2021 6:30 PM, Ansuel Smith wrote:
Future proof commit. This switch have 2 CPU port
Plural: ports.
and one valid
configuration is first CPU port set to sgmii and second CPU port set to
regmii-id.
rgmii-id
The current implementation detects delay only for CPU port
zero set to rgmii and doesn't count any delay set in a secondary CPU
port. Drop the current delay scan function and move it to the sgmii
parser function to generilize
generalize
and implicitly add support for secondary
CPU port set to rgmii-id. Introduce new logic where delay is enabled
also with internal delay binding declared and rgmii set as PHY mode.
Signed-off-by: Ansuel Smith <ansuelsmth@xxxxxxxxx>
Otherwise, looking good to me.
--
Florian
