On Sun, Oct 10, 2021 at 01:15:45PM +0200, Ansuel Smith wrote:
> Add support for this in the qca8k driver. Also add support for SGMII
> rx/tx clock falling edge. This is only present for pad0, pad5 and
> pad6 have these bit reserved from Documentation. Add a comment that this
> is hardcoded to PAD0 as qca8327/28/34/37 have an unique sgmii line and
> setting falling in port0 applies to both configuration with sgmii used
> for port0 or port6.
>
> Signed-off-by: Matthew Hagan <mnhagan88@xxxxxxxxx>
> Signed-off-by: Ansuel Smith <ansuelsmth@xxxxxxxxx>
> ---
> drivers/net/dsa/qca8k.c | 25 +++++++++++++++++++++++++
> drivers/net/dsa/qca8k.h | 3 +++
> 2 files changed, 28 insertions(+)
>
> diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
> index a892b897cd0d..3e4a12d6d61c 100644
> --- a/drivers/net/dsa/qca8k.c
> +++ b/drivers/net/dsa/qca8k.c
> @@ -1172,6 +1172,7 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
> const struct phylink_link_state *state)
> {
> struct qca8k_priv *priv = ds->priv;
> + struct dsa_port *dp;
> u32 reg, val;
> int ret;
>
> @@ -1240,6 +1241,8 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
> break;
> case PHY_INTERFACE_MODE_SGMII:
> case PHY_INTERFACE_MODE_1000BASEX:
> + dp = dsa_to_port(ds, port);
> +
> /* Enable SGMII on the port */
> qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
>
> @@ -1274,6 +1277,28 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
> }
>
> qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);
> +
> + /* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and
> + * falling edge is set writing in the PORT0 PAD reg
> + */
> + if (priv->switch_id == QCA8K_ID_QCA8327 ||
> + priv->switch_id == QCA8K_ID_QCA8337)
> + reg = QCA8K_REG_PORT0_PAD_CTRL;
> +
> + val = 0;
> +
> + /* SGMII Clock phase configuration */
> + if (of_property_read_bool(dp->dn, "qca,sgmii-rxclk-falling-edge"))
I would strongly recommend that you stop accessing dp->dn and add your
own device tree parsing function during probe time. It is also a runtime
invariant, there is no reason to read the device tree during each mac_config.
> + val |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE;
> +
> + if (of_property_read_bool(dp->dn, "qca,sgmii-txclk-falling-edge"))
> + val |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE;
> +
> + if (val)
> + ret = qca8k_rmw(priv, reg,
> + QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |
> + QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,
> + val);
> break;
> default:
> dev_err(ds->dev, "xMII mode %s not supported for port %d\n",
> diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h
> index fc7db94cc0c9..3fded69a6839 100644
> --- a/drivers/net/dsa/qca8k.h
> +++ b/drivers/net/dsa/qca8k.h
> @@ -35,6 +35,9 @@
> #define QCA8K_MASK_CTRL_DEVICE_ID_MASK GENMASK(15, 8)
> #define QCA8K_MASK_CTRL_DEVICE_ID(x) ((x) >> 8)
> #define QCA8K_REG_PORT0_PAD_CTRL 0x004
> +#define QCA8K_PORT0_PAD_CTRL_MAC06_EXCHG BIT(31)
QCA8K_PORT0_PAD_CTRL_MAC06_EXCHG is not used in this patch.
> +#define QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE BIT(19)
> +#define QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE BIT(18)
> #define QCA8K_REG_PORT5_PAD_CTRL 0x008
> #define QCA8K_REG_PORT6_PAD_CTRL 0x00c
> #define QCA8K_PORT_PAD_RGMII_EN BIT(26)
> --
> 2.32.0
>
