The CN9130-CRB boards have a MV88E6393X switch connected to eth0. Add
the necessary dts nodes and properties for this.
Signed-off-by: Chris Packham <chris.packham@xxxxxxxxxxxxxxxxxxx>
---
This is taken from the Marvell SDK. I've re-ordered the port entries to
be in ascending order.
arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 125 ++++++++++++++++++++
1 file changed, 125 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
index e7918f325646..171f7394948e 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
+++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
@@ -185,6 +185,131 @@ &cp0_mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
+
+ switch6: switch0@6 {
+ /* Actual device is MV88E6393X */
+ compatible = "marvell,mv88e6190";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+
+ dsa,member = <0 0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "notused-port0";
+ phy-mode = "10gbase-kr";
+ status = "disabled";
+
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "wan1";
+ phy-handle = <&switch0phy1>;
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan2";
+ phy-handle = <&switch0phy2>;
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan3";
+ phy-handle = <&switch0phy3>;
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan4";
+ phy-handle = <&switch0phy4>;
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "lan5";
+ phy-handle = <&switch0phy5>;
+ };
+
+ port@6 {
+ reg = <6>;
+ label = "lan6";
+ phy-handle = <&switch0phy6>;
+ };
+
+ port@7 {
+ reg = <7>;
+ label = "lan7";
+ phy-handle = <&switch0phy7>;
+ };
+
+ port@8 {
+ reg = <8>;
+ label = "lan8";
+ phy-handle = <&switch0phy8>;
+ };
+
+ port@9 {
+ reg = <9>;
+ label = "wanp9";
+ phy-mode = "10gbase-kr";
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ };
+ };
+
+ port@10 {
+ reg = <10>;
+ label = "cpu";
+ ethernet = <&cp0_eth0>;
+ };
+
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch0phy1: switch0phy1@1 {
+ reg = <0x1>;
+ };
+
+ switch0phy2: switch0phy2@2 {
+ reg = <0x2>;
+ };
+
+ switch0phy3: switch0phy3@3 {
+ reg = <0x3>;
+ };
+
+ switch0phy4: switch0phy4@4 {
+ reg = <0x4>;
+ };
+
+ switch0phy5: switch0phy5@5 {
+ reg = <0x5>;
+ };
+
+ switch0phy6: switch0phy6@6 {
+ reg = <0x6>;
+ };
+
+ switch0phy7: switch0phy7@7 {
+ reg = <0x7>;
+ };
+
+ switch0phy8: switch0phy8@8 {
+ reg = <0x8>;
+ };
+ };
+ };
};
&cp0_xmdio {
--
2.33.0
