Some qca8327 switch require the power_on_sel enabled for the pws_reg or
sets the led to open drain.
Also qca8327 switch have a special mode to declare reduced 48pin layout.
This special mode is only present in qca8327 as qca8337 have a different
pws_reg table.
Introduce a new binding and support these special configuration.
Signed-off-by: Ansuel Smith <ansuelsmth@xxxxxxxxx>
---
drivers/net/dsa/qca8k.c | 26 ++++++++++++++++++++++++++
drivers/net/dsa/qca8k.h | 3 +++
2 files changed, 29 insertions(+)
diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
index 01b05dfeae2b..209f8d3c9ea8 100644
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -1014,6 +1014,28 @@ qca8k_setup_port0_pad_ctrl_reg(struct qca8k_priv *priv)
return ret;
}
+static int
+qca8k_setup_of_pws_reg(struct qca8k_priv *priv)
+{
+ struct device_node *node = priv->dev->of_node;
+ u32 val = 0;
+
+ if (priv->switch_id == QCA8K_ID_QCA8327)
+ if (of_property_read_bool(node, "qca,package48"))
+ val |= QCA8327_PWS_PACKAGE48_EN;
+
+ if (of_property_read_bool(node, "qca,power-on-sel"))
+ val |= QCA8K_PWS_POWER_ON_SEL;
+
+ if (of_property_read_bool(node, "qca,led-open-drain"))
+ /* POWER_ON_SEL needs to be set when configuring led to open drain */
+ val |= QCA8K_PWS_LED_OPEN_EN_CSR | QCA8K_PWS_POWER_ON_SEL;
+
+ return qca8k_rmw(priv, QCA8K_REG_PWS,
+ QCA8K_PWS_LED_OPEN_EN_CSR | QCA8K_PWS_POWER_ON_SEL,
+ val);
+}
+
static int
qca8k_setup(struct dsa_switch *ds)
{
@@ -1039,6 +1061,10 @@ qca8k_setup(struct dsa_switch *ds)
if (ret)
return ret;
+ ret = qca8k_setup_of_pws_reg(priv);
+ if (ret)
+ return ret;
+
ret = qca8k_setup_of_rgmii_delay(priv);
if (ret)
return ret;
diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h
index 3fded69a6839..90f4616c33f1 100644
--- a/drivers/net/dsa/qca8k.h
+++ b/drivers/net/dsa/qca8k.h
@@ -48,6 +48,9 @@
#define QCA8K_MAX_DELAY 3
#define QCA8K_PORT_PAD_SGMII_EN BIT(7)
#define QCA8K_REG_PWS 0x010
+#define QCA8K_PWS_POWER_ON_SEL BIT(31)
+#define QCA8327_PWS_PACKAGE48_EN BIT(30)
+#define QCA8K_PWS_LED_OPEN_EN_CSR BIT(24)
#define QCA8K_PWS_SERDES_AEN_DIS BIT(7)
#define QCA8K_REG_MODULE_EN 0x030
#define QCA8K_MODULE_EN_MIB BIT(0)
--
2.32.0
