On 2021-09-20 18:56, Chen-Yu Tsai wrote:
From: Chen-Yu Tsai <wens@xxxxxxxx>
The RK3399 does not seem to be able to properly generate the required
64 MHz clock for the UART to operate at 4MBd.
Drop the baud rate down to 3MBd, which can be used as the clock
controller is able to produce a 48 MHz clock.
Hmm, I've been running mine this way (with DMA) for ages now :/
Looking at clk_summary, clk_uart0_src ends up at 800MHz off CPLL (same
as several other significant clocks), with clk_uart0 at an exact 64MHz
as a division of that. I stuck a scope on the UART pins of the module
and all the edges look nicely lined up to 250ns intervals.
This is with a 5.11.4 kernel, though - I wonder if the recent fractional
divider changes in the clock driver have changed anything?
Robin.
Fixes: 3e2f0bb72be3 ("arm64: dts: rockchip: Add nanopi4 bluetooth")
Signed-off-by: Chen-Yu Tsai <wens@xxxxxxxx>
---
arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
index 8c0ff6c96e03..45ff053b119d 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
@@ -699,7 +699,7 @@ bluetooth {
device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
- max-speed = <4000000>;
+ max-speed = <3000000>;
pinctrl-names = "default";
pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>;
vbat-supply = <&vcc3v3_sys>;
