Quoting Prasad Malisetty (2021-10-04 12:41:26)
> Enable PCIe controller and PHY for sc7280 IDP board.
> Add specific NVMe GPIO entries for SKU1 and SKU2 support.
>
> Signed-off-by: Prasad Malisetty <pmaliset@xxxxxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/sc7280-idp.dts | 8 +++++
> arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 51 ++++++++++++++++++++++++++++++++
> arch/arm64/boot/dts/qcom/sc7280-idp2.dts | 8 +++++
> 3 files changed, 67 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
> index 272d5ca..b416f3d 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
> @@ -462,6 +491,28 @@
> };
>
> &tlmm {
> + nvme_pwren_pin: nvme-pwren-pin {
pin is sort of redundant but OK. It would be simpler without the pin
postfix.
> + function = "gpio";
> + bias-pull-up;
Why is there a bias pull up on this enable pin? I'd expect to see a
bias-disable as this is an output pin and there's no need for a pull.
> + };
> +
> + pcie1_reset_n: pcie1-reset-n {
> + pins = "gpio2";
> + function = "gpio";
> +
> + drive-strength = <16>;
Why such a strong drive strength?
> + output-low;
> + bias-disable;
> + };
> +
> + pcie1_wake_n: pcie1-wake-n {
> + pins = "gpio3";
> + function = "gpio";
> +
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> qup_uart7_sleep_cts: qup-uart7-sleep-cts {
> pins = "gpio28";
> function = "gpio";
