Some Tegra20 boards don't have RAM code stored in NVMEM, which is used for
the memory chip identification and the identity information should be read
out from LPDDR2 chip in this case. Document new sub-node containing generic
LPDDR2 properties that will be used for the memory chip identification if
RAM code isn't available. The identification is done by reading out memory
configuration values from generic LPDDR2 mode registers of SDRAM chip and
comparing them with the values of device-tree sub-node's.
Signed-off-by: Dmitry Osipenko <digetx@xxxxxxxxx>
---
.../memory-controllers/nvidia,tegra20-emc.yaml | 17 ++++++++++++++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml
index cac6842dc8f1..2741333591bf 100644
--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml
@@ -164,13 +164,14 @@ patternProperties:
"#size-cells":
const: 0
+ lpddr2-configuration:
+ $ref: "jedec,lpddr2.yaml#"
+ type: object
+
patternProperties:
"^emc-table@[0-9]+$":
$ref: "#/$defs/emc-table"
- required:
- - nvidia,ram-code
-
additionalProperties: false
required:
@@ -186,6 +187,8 @@ additionalProperties: false
examples:
- |
+ #include <dt-bindings/memory/lpddr2.h>
+
external-memory-controller@7000f400 {
compatible = "nvidia,tegra20-emc";
reg = <0x7000f400 0x400>;
@@ -226,5 +229,13 @@ examples:
0x007fe010 0x00001414 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000>;
};
+
+ lpddr2-config {
+ jedec,lpddr2-manufacturer-id = <LPDDR2_MANID_ELPIDA>;
+ jedec,lpddr2-revision-id1 = <1>;
+ jedec,lpddr2-density-mbits = <2048>;
+ jedec,lpddr2-io-width-bits = <16>;
+ jedec,lpddr2-type = <LPDDR2_TYPE_S4>;
+ };
};
};
--
2.32.0
