On Wed, Sep 29, 2021 at 11:06 PM Sai Prakash Ranjan <saiprakash.ranjan@xxxxxxxxxxxxxx> wrote: > > On 2021-09-29 18:12, Rob Herring wrote: > > On Wed, Sep 29, 2021 at 12:26 AM Sai Prakash Ranjan > > <saiprakash.ranjan@xxxxxxxxxxxxxx> wrote: > >> > >> System Cache Controller (Last Level Cache Controller/LLCC) does not > >> have a cache-level associated with it as enforced by the already > >> existing 'cache-controller' node name, so add system-cache-controller > >> to the list of generic node names as decided on the lkml in [1][2] > >> and already being used in the dts for sometime now. > >> > >> [1] > >> https://lore.kernel.org/lkml/5dcd8588.1c69fb81.2528a.3460@xxxxxxxxxxxxx/ > >> [2] > >> https://lore.kernel.org/lkml/cover.1573814758.git.saiprakash.ranjan@xxxxxxxxxxxxxx/ > >> > >> Cc: Stephen Boyd <swboyd@xxxxxxxxxxxx> > >> Cc: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx> > >> Cc: Rajendra Nayak <rnayak@xxxxxxxxxxxxxx> > >> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@xxxxxxxxxxxxxx> > >> --- > >> source/chapter2-devicetree-basics.rst | 1 + > >> 1 file changed, 1 insertion(+) > >> > >> diff --git a/source/chapter2-devicetree-basics.rst > >> b/source/chapter2-devicetree-basics.rst > >> index 40be22192b2f..c06c5063c68b 100644 > >> --- a/source/chapter2-devicetree-basics.rst > >> +++ b/source/chapter2-devicetree-basics.rst > >> @@ -276,6 +276,7 @@ name should be one of the following choices: > >> * sram-controller > >> * ssi-controller > >> * syscon > >> + * system-cache-controller > > > > I don't want to encourage others to use this over 'cache-controller' > > and the standard binding. > > > > Right, but why would others use this over cache-controller? This is > supposed > to be used only for last level cache controllers where there is no > cache-level > associated with it like in the system cache controller/LLCC found in QTI > SoCs. I don't agree there's never a level. Using the cache binding will be necessary if you want to populate the kernel's cache info. If your caches have MPAM support, they are going to need to follow the cache binding as well. > Also you had acked the corresponding change in the DT binding for LLCC > [1]. Yes, but that doesn't mean it belongs in the spec. Maybe when we have more than 1 case that will change, but for now I don't think it should be in the spec. Rob
