Hi Neil,
> Am 28.09.2021 um 15:02 schrieb Neil Armstrong <narmstrong@xxxxxxxxxxxx>:
>
> On 27/09/2021 18:44, H. Nikolaus Schaller wrote:
>> From: Paul Boddie <paul@xxxxxxxxxxxxx>
>>
>> A specialisation of the generic Synopsys HDMI driver is employed for JZ4780
>> HDMI support. This requires a new driver, plus device tree and configuration
>> modifications.
>>
>> Signed-off-by: Paul Boddie <paul@xxxxxxxxxxxxx>
>> Signed-off-by: Ezequiel Garcia <ezequiel@xxxxxxxxxxxxx>
>> Signed-off-by: H. Nikolaus Schaller <hns@xxxxxxxxxxxxx>
>> ---
>> drivers/gpu/drm/ingenic/Kconfig | 9 ++
>> drivers/gpu/drm/ingenic/Makefile | 1 +
>> drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c | 142 ++++++++++++++++++++++
>> 3 files changed, 152 insertions(+)
>> create mode 100644 drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c
>>
>> diff --git a/drivers/gpu/drm/ingenic/Kconfig b/drivers/gpu/drm/ingenic/Kconfig
>> index 3b57f8be007c..4c7d311fbeff 100644
>> --- a/drivers/gpu/drm/ingenic/Kconfig
>> +++ b/drivers/gpu/drm/ingenic/Kconfig
>> @@ -25,4 +25,13 @@ config DRM_INGENIC_IPU
>>
>> The Image Processing Unit (IPU) will appear as a second primary plane.
>>
>> +config DRM_INGENIC_DW_HDMI
>> + bool "Ingenic specific support for Synopsys DW HDMI"
>> + depends on MACH_JZ4780
>> + select DRM_DW_HDMI
>> + help
>> + Choose this option to enable Synopsys DesignWare HDMI based driver.
>> + If you want to enable HDMI on Ingenic JZ4780 based SoC, you should
>> + select this option..
>> +
>> endif
>> diff --git a/drivers/gpu/drm/ingenic/Makefile b/drivers/gpu/drm/ingenic/Makefile
>> index d313326bdddb..3db9888a6c04 100644
>> --- a/drivers/gpu/drm/ingenic/Makefile
>> +++ b/drivers/gpu/drm/ingenic/Makefile
>> @@ -1,3 +1,4 @@
>> obj-$(CONFIG_DRM_INGENIC) += ingenic-drm.o
>> ingenic-drm-y = ingenic-drm-drv.o
>> ingenic-drm-$(CONFIG_DRM_INGENIC_IPU) += ingenic-ipu.o
>> +ingenic-drm-$(CONFIG_DRM_INGENIC_DW_HDMI) += ingenic-dw-hdmi.o
>> diff --git a/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c b/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c
>> new file mode 100644
>> index 000000000000..dd9c94ae842e
>> --- /dev/null
>> +++ b/drivers/gpu/drm/ingenic/ingenic-dw-hdmi.c
>> @@ -0,0 +1,142 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/* Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
>> + * Copyright (C) 2019, 2020 Paul Boddie <paul@xxxxxxxxxxxxx>
>> + *
>> + * Derived from dw_hdmi-imx.c with i.MX portions removed.
>> + * Probe and remove operations derived from rcar_dw_hdmi.c.
>> + */
>> +
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/regmap.h>
>> +
>> +#include <drm/bridge/dw_hdmi.h>
>> +#include <drm/drm_of.h>
>> +#include <drm/drm_print.h>
>> +
>> +static const struct dw_hdmi_mpll_config ingenic_mpll_cfg[] = {
>> + { 45250000, { { 0x01e0, 0x0000 }, { 0x21e1, 0x0000 }, { 0x41e2, 0x0000 } } },
>> + { 92500000, { { 0x0140, 0x0005 }, { 0x2141, 0x0005 }, { 0x4142, 0x0005 } } },
>> + { 148500000, { { 0x00a0, 0x000a }, { 0x20a1, 0x000a }, { 0x40a2, 0x000a } } },
>> + { 216000000, { { 0x00a0, 0x000a }, { 0x2001, 0x000f }, { 0x4002, 0x000f } } },
>> + { ~0UL, { { 0x0000, 0x0000 }, { 0x0000, 0x0000 }, { 0x0000, 0x0000 } } }
>> +};
>> +
>> +static const struct dw_hdmi_curr_ctrl ingenic_cur_ctr[] = {
>> + /*pixelclk bpp8 bpp10 bpp12 */
>> + { 54000000, { 0x091c, 0x091c, 0x06dc } },
>> + { 58400000, { 0x091c, 0x06dc, 0x06dc } },
>> + { 72000000, { 0x06dc, 0x06dc, 0x091c } },
>> + { 74250000, { 0x06dc, 0x0b5c, 0x091c } },
>> + { 118800000, { 0x091c, 0x091c, 0x06dc } },
>> + { 216000000, { 0x06dc, 0x0b5c, 0x091c } },
>> + { ~0UL, { 0x0000, 0x0000, 0x0000 } },
>> +};
>> +
>> +/*
>> + * Resistance term 133Ohm Cfg
>> + * PREEMP config 0.00
>> + * TX/CK level 10
>> + */
>> +static const struct dw_hdmi_phy_config ingenic_phy_config[] = {
>> + /*pixelclk symbol term vlev */
>> + { 216000000, 0x800d, 0x0005, 0x01ad},
>> + { ~0UL, 0x0000, 0x0000, 0x0000}
>> +};
>> +
>> +static enum drm_mode_status
>> +ingenic_dw_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data,
>> + const struct drm_display_info *info,
>> + const struct drm_display_mode *mode)
>> +{
>> + if (mode->clock < 13500)
>> + return MODE_CLOCK_LOW;
>> + /* FIXME: Hardware is capable of 270MHz, but setup data is missing. */
>> + if (mode->clock > 216000)
>> + return MODE_CLOCK_HIGH;
>> +
>> + return MODE_OK;
>> +}
>> +
>> +static bool
>> +ingenic_dw_hdmi_mode_fixup(struct drm_bridge *bridge,
>> + const struct drm_display_mode *mode,
>> + struct drm_display_mode *adjusted_mode)
>> +{
>> + adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
>> + adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
>> +
>> + return true;
>> +}
>> +
>> +static const struct drm_bridge_timings ingenic_dw_hdmi_timings = {
>> + .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
>> +};
>
> These should go in the intermediate encoder bridge callbacks Paul introduces in his patch at [1].
>
> With that patch 4 can be dropped.
>
> [1] https://lore.kernel.org/r/20210922205555.496871-7-paul@xxxxxxxxxxxxxxx
>
> Neil
Sorry, but I can't follow you here. Our patch set is on top of Paul's patch [1]
and requires Paul's work to be merged first.
And our 4/10 is needed to specialize dw-hdmi to the jz4780 like it is done for
other SoC integration. It addresses a different stage of the jz4780 HDMI chain
than [1].
BR,
Nikolaus
