Re: [PATCH v4 04/10] PCI: apple: Add initial hardware bring-up

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On Wed, 22 Sep 2021 22:08:33 +0100,
"Sven Peter" <sven@xxxxxxxxxxxxx> wrote:
> 
> Hi,
> 
> 
> On Wed, Sep 22, 2021, at 22:54, Marc Zyngier wrote:
> > From: Alyssa Rosenzweig <alyssa@xxxxxxxxxxxxx>
> >
> [...]
> > +
> > +	/* Use the first reg entry to work out the port index */
> > +	port->idx = idx >> 11;
> > +	port->pcie = pcie;
> > +	port->np = np;
> > +
> > +	port->base = devm_platform_ioremap_resource(platform, port->idx + 2);
> > +	if (IS_ERR(port->base))
> > +		return -ENODEV;
> > +
> > +	rmw_set(PORT_APPCLK_EN, port + PORT_APPCLK);
> 
> I think this should be
> 
>     rmw_set(PORT_APPCLK_EN, port->base + PORT_APPCLK);

Ouch. Well caught. I wonder how many of these I introduced...:-/

> 
> > +
> > +	rmw_set(PORT_PERST_OFF, port->base + PORT_PERST);
> > +	gpiod_set_value(reset, 1);
> > +
> > +	ret = readl_relaxed_poll_timeout(port->base + PORT_STATUS, stat,
> > +					 stat & PORT_STATUS_READY, 100, 250000);
> > +	if (ret < 0) {
> > +		dev_err(pcie->dev, "port %pOF ready wait timeout\n", np);
> > +		return ret;
> > +	}
> > +
> > +	/* Flush writes and enable the link */
> > +	dma_wmb();
> 
> I don't think this barrier is required.

It really isn't, and I though I had removed it. I now wonder whether I
have pushed out the right branch, or messed up by moving from one
machine to another...

> > +
> > +	writel_relaxed(PORT_LTSSMCTL_START, port->base + PORT_LTSSMCTL);
> > +
> > +	return 0;
> > +}
> > +
> [...]
> 
> 
> Looks good to me otherwise,
> 
> Reviewed-by: Sven Peter <sven@xxxxxxxxxxxxx>

Thanks. Hopefully I'll manage to post a non broken series next time...

	M.

-- 
Without deviation from the norm, progress is not possible.



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