On Tue, 14 Sep 2021 19:36:52 +0800, Yong Wu wrote: > Add the binding for smi-sub-common. The SMI block diagram like this: > > IOMMU > | | > smi-common > ------------------ > | .... | > larb0 larb7 <-max is 8 > > The smi-common connects with smi-larb and IOMMU. The maximum larbs number > that connects with a smi-common is 8. If the engines number is over 8, > sometimes we use a smi-sub-common which is nearly same with smi-common. > It supports up to 8 input and 1 output(smi-common has 2 output) > > Something like: > > IOMMU > | | > smi-common > --------------------- > | | ... > larb0 sub-common ... <-max is 8 > ----------- > | | ... <-max is 8 too. > larb2 larb5 > > We don't need extra SW setting for smi-sub-common, only the sub-common has > special clocks need to enable when the engines access dram. > > If it is sub-common, it should have a "mediatek,smi" phandle to point to > its smi-common. meanwhile the sub-common only has one gals clock. > > Signed-off-by: Yong Wu <yong.wu@xxxxxxxxxxxx> > --- > change note: add "else mediatek,smi: false". > --- > .../mediatek,smi-common.yaml | 28 +++++++++++++++++++ > 1 file changed, 28 insertions(+) > Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
