Re: [PATCH V8 4/8] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes

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On 2021-09-21 01:12, Stephen Boyd wrote:
Quoting Rajesh Patil (2021-09-17 02:48:03)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 2fbcb0a..a2a4d7e 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -536,24 +536,444 @@
                qupv3_id_0: geniqup@9c0000 {
                        compatible = "qcom,geni-se-qup";
                        reg = <0 0x009c0000 0 0x2000>;
-                       clock-names = "m-ahb", "s-ahb";
                        clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
                                 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+                       clock-names = "m-ahb", "s-ahb";
                        #address-cells = <2>;
                        #size-cells = <2>;
                        ranges;
+                       iommus = <&apps_smmu 0x123 0x0>;
                        status = "disabled";

+                       qup_opp_table: qup-opp-table {

Sorry to mislead you. I see now why it can't be here. qeniqup has
address cells and size cells not equal to zero, which means that every
child node of qeniqup should have a reg property. So this OPP table
needs to be moved to the root again (ugh).

Okay


+                               compatible = "operating-points-v2";
+
+                               opp-75000000 {
+                                       opp-hz = /bits/ 64 <75000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+                               };
+
+                               opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>;
+                               };
+
+                               opp-128000000 {
+ opp-hz = /bits/ 64 <128000000>; + required-opps = <&rpmhpd_opp_nom>;
+                               };
+                       };
+
+                       i2c0: i2c@980000 {
+                               compatible = "qcom,geni-i2c";
+                               reg = <0 0x00980000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+                               clock-names = "se";
+                               pinctrl-names = "default";
[...]

                cnoc2: interconnect@1500000 {
@@ -1574,11 +1994,311 @@
                                function = "qspi_data";
[...]
+
+                       qup_spi0_cs_gpio: qup-spi0-cs_gpio {

Please make it "qup_spi0_cs_gpio: qup-spi0-cs-gpio" as node names should
have dashes instead of underscores.

Okay


+                               pins = "gpio3";



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