On Mon, 20 Sep 2021 15:25:59 +0200, Krzysztof Kozlowski wrote:
> All existing boards with sifive,e51 and sifive,u54-mc use it on top of
> sifive,rocket0 compatible:
>
> arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml: cpu@0: compatible: 'oneOf' conditional failed, one must be fixed:
> ['sifive,e51', 'sifive,rocket0', 'riscv'] is too long
> Additional items are not allowed ('riscv' was unexpected)
> Additional items are not allowed ('sifive,rocket0', 'riscv' were unexpected)
> 'riscv' was expected
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxxxxx>
>
> ---
>
> Hi Rob,
>
> You previously acked this patch but I think it will be easier if you
> take it directly.
>
> Best regards,
> Krzysztof
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
Applied, thanks!
