Re: [PATCH v2 2/4] dt-bindings: clk: sprd: Add bindings for ums512 clock controller

[Rob Herring <robh@xxxxxxxxxx>]

On Thu, Sep 16, 2021 at 04:47:12PM +0800, Chunyan Zhang wrote:
> From: Chunyan Zhang <chunyan.zhang@xxxxxxxxxx>
> 
> Add a new bindings to describe ums512 clock compatible strings.
> 
> Signed-off-by: Chunyan Zhang <chunyan.zhang@xxxxxxxxxx>
> ---
>  .../bindings/clock/sprd,ums512-clk.yaml       | 106 ++++++++++++++++++
>  1 file changed, 106 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml
> 
> diff --git a/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml b/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml
> new file mode 100644
> index 000000000000..be3c37180279
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml
> @@ -0,0 +1,106 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright 2019-2021 Unisoc Inc.
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/clock/sprd,ums512-clk.yaml#";
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#";
> +
> +title: UMS512 Clock Control Unit Device Tree Bindings
> +
> +maintainers:
> +  - Orson Zhai <orsonzhai@xxxxxxxxx>
> +  - Baolin Wang <baolin.wang7@xxxxxxxxx>
> +  - Chunyan Zhang <zhang.lyra@xxxxxxxxx>
> +
> +properties:
> +  "#clock-cells":
> +    const: 1
> +
> +  compatible:
> +    enum:
> +      - sprd,ums512-apahb-gate
> +      - sprd,ums512-ap-clk
> +      - sprd,ums512-aonapb-clk
> +      - sprd,ums512-pmu-gate
> +      - sprd,ums512-g0-pll
> +      - sprd,ums512-g2-pll
> +      - sprd,ums512-g3-pll
> +      - sprd,ums512-gc-pll
> +      - sprd,ums512-aon-gate
> +      - sprd,ums512-audcpapb-gate
> +      - sprd,ums512-audcpahb-gate
> +      - sprd,ums512-gpu-clk
> +      - sprd,ums512-mm-clk
> +      - sprd,ums512-mm-gate-clk
> +      - sprd,ums512-apapb-gate
> +
> +  clocks:
> +    minItems: 1
> +    maxItems: 4
> +    description: |
> +      The input parent clock(s) phandle for this clock, only list fixed
> +      clocks which are declared in devicetree.
> +
> +  clock-names:
> +    minItems: 1
> +    maxItems: 4
> +    items:
> +      - const: ext-26m
> +      - const: ext-32k
> +      - const: ext-4m
> +      - const: rco-100m
> +
> +  reg:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - '#clock-cells'
> +
> +if:
> +  properties:
> +    compatible:
> +      enum:
> +        - sprd,ums512-ap-clk
> +        - sprd,ums512-aonapb-clk
> +        - sprd,ums512-mm-clk
> +then:
> +  required:
> +    - reg
> +
> +else:
> +  description: |
> +    Other UMS512 clock nodes should be the child of a syscon node in
> +    which compatible string should be:
> +            "sprd,ums512-glbregs", "syscon", "simple-mfd"
> +
> +    The 'reg' property for the clock node is also required if there is a sub
> +    range of registers for the clocks.

In which cases is this not true?

> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    ap_clk: clock-controller@20200000 {
> +      compatible = "sprd,ums512-ap-clk";
> +      reg = <0x20200000 0x1000>;
> +      clocks = <&ext_26m>;
> +      clock-names = "ext-26m";
> +      #clock-cells = <1>;
> +    };
> +
> +  - |
> +    ap_apb_regs: syscon@71000000 {
> +      compatible = "sprd,ums512-glbregs", "syscon", "simple-mfd";
> +      reg = <0x71000000 0x3000>;
> +      #address-cells = <1>;
> +      #size-cells = <1>;
> +      ranges = <0 0x71000000 0x3000>;
> +
> +      apahb_gate: clock-controller@0 {
> +        compatible = "sprd,ums512-apahb-gate";
> +        reg = <0x0 0x2000>;
> +        #clock-cells = <1>;
> +      };

We have this example in the MFD schema, so drop it here.