On Tue 14 Sep 18:13 PDT 2021, Stephen Boyd wrote:
> Quoting Prasad Malisetty (2021-09-14 11:19:09)
> > Enable PCIe controller and PHY for sc7280 IDP board.
> > Add specific NVMe GPIO entries for SKU1 and SKU2 support.
> >
> > Signed-off-by: Prasad Malisetty <pmaliset@xxxxxxxxxxxxxx>
> > ---
> > arch/arm64/boot/dts/qcom/sc7280-idp.dts | 9 +++++++++
> > arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 32 ++++++++++++++++++++++++++++++++
> > arch/arm64/boot/dts/qcom/sc7280-idp2.dts | 9 +++++++++
> > 3 files changed, 50 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> > index 64fc22a..2cc6b0a 100644
> > --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> > +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> > @@ -61,6 +61,15 @@
> > modem-init;
> > };
> >
> > +&pcie1_default_state {
> > + nvme-n {
> > + pins = "gpio19";
> > + function = "gpio";
> > +
> > + bias-pull-up;
> > + };
>
> I don't think the style is to have a single container node anymore.
> Instead, each pin gets a different node and then pinctrl-0 has a list of
> phandles to the different nodes. qcom maintainers may have more input
> here.
>
Having a container that defines the state and each part thereof is
preferred (see other PCIe users or how we typically define the Bluetooth
UART). But is "nvme_n" really part of the "PCI state" or is this related
to the NVME device instead?
> Also, this should really go into a different section than here. I
> thought the style was to have a 'board specific' pinctrl section.
>
Yes, pushing pinctrl states to the bottom is preferred and rather than
amending the existing state I think this goes in a state of its own and
the pinctrl-N amended to include this new state as well.
Regards,
Bjorn
> > +};
> > +
> > &pmk8350_vadc {
> > pmr735a_die_temp {
> > reg = <PMR735A_ADC7_DIE_TEMP>;
