On Thu, 02 Sep 2021 17:57:48 -0500, Samuel Holland wrote: > On existing SoCs, the watchdog has a single clock input: HOSC (OSC24M) > divided by 750. However, starting with R329, LOSC (OSC32k) is added as > an alternative clock source, with a bit to switch between them. > > Since 24 MHz / 750 == 32 kHz, not 32.768 kHz, the hardware adjusts the > cycle counts to keep the timeouts independent of the clock source. This > keeps the programming interface backward-compatible. > > Furthermore, the R329 has two watchdogs: one for use by the ARM CPUs > at 0x20000a0, and a second one for use by the DSPs at 0x7020400. The > first of these adds two more new registers, to allow software to > immediately assert the SoC reset signal. Add an additional "-reset" > suffix to signify the presence of this feature. > > Signed-off-by: Samuel Holland <samuel@xxxxxxxxxxxx> > --- > Changes v2 to v3: > - Add else case > - Add additional allwinner,sun50i-r329-wdt-reset compatible > Changes v1 to v2: > - Switch clock-names from enum to const > - Add descriptions to "clocks" items > > .../watchdog/allwinner,sun4i-a10-wdt.yaml | 42 ++++++++++++++++++- > 1 file changed, 41 insertions(+), 1 deletion(-) > Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
