Cadence Sierra PHY is a multiprotocol PHY supporting different multilink
PHY configurations. This patch series extends functionality of Sierra PHY
driver by adding features like support for multilink multiprotocol
configurations, derived reference clock etc.
The changes have been validated on TI J721E platform.
Swapnil Jakhade (14):
phy: cadence: Sierra: Use of_device_get_match_data() to get driver
data
phy: cadence: Sierra: Prepare driver to add support for multilink
configurations
dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode
phy: cadence: Sierra: Add support to get SSC type from device tree
phy: cadence: Sierra: Rename some regmap variables to be in sync with
Sierra documentation
phy: cadence: Sierra: Add PHY PCS common register configurations
phy: cadence: Sierra: Check cmn_ready assertion during PHY power on
phy: cadence: Sierra: Check PIPE mode PHY status to be ready for
operation
phy: cadence: Sierra: Update single link PCIe register configuration
phy: cadence: Sierra: Fix to get correct parent for mux clocks
phy: cadence: Sierra: Add support for PHY multilink configurations
phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration
dt-bindings: phy: cadence-sierra: Add clock ID for derived reference
clock
phy: cadence: Sierra: Add support for derived reference clock output
.../bindings/phy/phy-cadence-sierra.yaml | 9 +
drivers/phy/cadence/phy-cadence-sierra.c | 1299 +++++++++++++++--
include/dt-bindings/phy/phy-cadence.h | 5 +
3 files changed, 1224 insertions(+), 89 deletions(-)
--
2.26.1
