On Wed, 1 Sept 2021 at 14:12, Tanmay Jagdale <tanmay@xxxxxxxxxxx> wrote: > > The current driver sets the write burst size initiated by TMC-ETR on > AXI bus to a fixed value of 16. Make this configurable by reading the > value specified in fwnode. If not specified, then default to 16. > > Introduced a "max_burst_size" variable in tmc_drvdata structure to > facilitate this change. > > Signed-off-by: Tanmay Jagdale <tanmay@xxxxxxxxxxx> > --- > .../hwtracing/coresight/coresight-tmc-core.c | 21 +++++++++++++++++-- > .../hwtracing/coresight/coresight-tmc-etr.c | 3 ++- > drivers/hwtracing/coresight/coresight-tmc.h | 6 +++++- > 3 files changed, 26 insertions(+), 4 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c > index 74c6323d4d6a..d0276af82494 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-core.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c > @@ -432,6 +432,21 @@ static u32 tmc_etr_get_default_buffer_size(struct device *dev) > return size; > } > > +static u32 tmc_etr_get_max_burst_size(struct device *dev) > +{ > + u32 burst_size; > + > + if (fwnode_property_read_u32(dev->fwnode, "arm,max-burst-size", > + &burst_size)) > + return TMC_AXICTL_WR_BURST_16; > + > + /* Only permissible values are 0 to 15 */ > + if (burst_size > 0xF) > + burst_size = TMC_AXICTL_WR_BURST_16; > + > + return burst_size; > +} > + > static int tmc_probe(struct amba_device *adev, const struct amba_id *id) > { > int ret = 0; > @@ -469,10 +484,12 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id) > /* This device is not associated with a session */ > drvdata->pid = -1; > > - if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) > + if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) { > drvdata->size = tmc_etr_get_default_buffer_size(dev); > - else > + drvdata->max_burst_size = tmc_etr_get_max_burst_size(dev); > + } else { > drvdata->size = readl_relaxed(drvdata->base + TMC_RSZ) * 4; > + } > > desc.dev = dev; > desc.groups = coresight_tmc_groups; > diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c > index acdb59e0e661..0ac2a611110b 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c > @@ -982,7 +982,8 @@ static void __tmc_etr_enable_hw(struct tmc_drvdata *drvdata) > > axictl = readl_relaxed(drvdata->base + TMC_AXICTL); > axictl &= ~TMC_AXICTL_CLEAR_MASK; > - axictl |= (TMC_AXICTL_PROT_CTL_B1 | TMC_AXICTL_WR_BURST_16); > + axictl |= TMC_AXICTL_PROT_CTL_B1; > + axictl |= TMC_AXICTL_WR_BURST(drvdata->max_burst_size); > axictl |= TMC_AXICTL_AXCACHE_OS; > > if (tmc_etr_has_cap(drvdata, TMC_ETR_AXI_ARCACHE)) { > diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h > index b91ec7dde7bc..6bec20a392b3 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc.h > +++ b/drivers/hwtracing/coresight/coresight-tmc.h > @@ -70,7 +70,8 @@ > #define TMC_AXICTL_PROT_CTL_B0 BIT(0) > #define TMC_AXICTL_PROT_CTL_B1 BIT(1) > #define TMC_AXICTL_SCT_GAT_MODE BIT(7) > -#define TMC_AXICTL_WR_BURST_16 0xF00 > +#define TMC_AXICTL_WR_BURST(v) (((v) & 0xf) << 8) > +#define TMC_AXICTL_WR_BURST_16 0xf > /* Write-back Read and Write-allocate */ > #define TMC_AXICTL_AXCACHE_OS (0xf << 2) > #define TMC_AXICTL_ARCACHE_OS (0xf << 16) > @@ -174,6 +175,8 @@ struct etr_buf { > * @etr_buf: details of buffer used in TMC-ETR > * @len: size of the available trace for ETF/ETB. > * @size: trace buffer size for this TMC (common for all modes). > + * @max_burst_size: The maximum burst size that can be initiated by > + * TMC-ETR on AXI bus. > * @mode: how this TMC is being used. > * @config_type: TMC variant, must be of type @tmc_config_type. > * @memwidth: width of the memory interface databus, in bytes. > @@ -198,6 +201,7 @@ struct tmc_drvdata { > }; > u32 len; > u32 size; > + u32 max_burst_size; > u32 mode; > enum tmc_config_type config_type; > enum tmc_mem_intf_width memwidth; > -- > 2.25.1 > Reviewed-by: Mike Leach <mike.leach@xxxxxxxxxx> -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK