On 25/08/2021 14:06, Krzysztof Kozlowski wrote:
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>
> The Microchip Icicle kit uses SiFive E51 and U54 cores, so it looks that
> also Core Local Interruptor and Platform-Level Interrupt Controller are
> coming from SiFive. Add proper compatibles to silence dtbs_check
> warnings:
>
> clint@2000000: compatible:0: 'sifive,clint0' is not one of ['sifive,fu540-c000-clint', 'canaan,k210-clint']
> interrupt-controller@c000000: compatible:0: 'sifive,plic-1.0.0' is not one of ['sifive,fu540-c000-plic', 'canaan,k210-plic']
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxxxxx>
>
> ---
>
> Changes since v1:
> 1. None
> ---
> arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> index d9f7ee747d0d..6f843afacfad 100644
> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> @@ -161,7 +161,7 @@ cache-controller@2010000 {
> };
>
> clint@2000000 {
> - compatible = "sifive,clint0";
> + compatible = "sifive,fu540-c000-clint", "sifive,clint0";
> reg = <0x0 0x2000000 0x0 0xC000>;
> interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
> &cpu1_intc 3 &cpu1_intc 7
> @@ -172,7 +172,7 @@ &cpu3_intc 3 &cpu3_intc 7
>
> plic: interrupt-controller@c000000 {
> #interrupt-cells = <1>;
> - compatible = "sifive,plic-1.0.0";
> + compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
> reg = <0x0 0xc000000 0x0 0x4000000>;
> riscv,ndev = <186>;
> interrupt-controller;
> --
> 2.30.2
>
Looks good, we've switched to using this one ourselves also.
Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
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