Hi, Thanks for your review. On Sat, Aug 28, 2021 at 10:09:54PM -0700, Stephen Boyd wrote: > Quoting Nobuhiro Iwamatsu (2021-08-04 02:22:41) > > Add device tree bindings for PLL of Toshiba Visconti TMPV770x SoC series. > > > > Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@xxxxxxxxxxxxx> > > --- > > .../clock/toshiba,tmpv770x-pipllct.yaml | 57 +++++++++++++++++++ > > 1 file changed, 57 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pipllct.yaml > > > > diff --git a/Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pipllct.yaml b/Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pipllct.yaml > > new file mode 100644 > > index 000000000000..7b7300ce96d6 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pipllct.yaml > > @@ -0,0 +1,57 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/clock/toshiba,tmpv770x-pipllct.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Toshiba Visconti5 TMPV770X PLL Controller Device Tree Bindings > > + > > +maintainers: > > + - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@xxxxxxxxxxxxx> > > + > > +description: > > + Toshia Visconti5 PLL controller which supports the PLLs on TMPV770X. > > + > > +properties: > > + compatible: > > + const: toshiba,tmpv7708-pipllct > > + > > + reg: > > + maxItems: 1 > > + > > + '#clock-cells': > > + const: 1 > > + > > + clocks: > > + description: External reference clock (OSC2) > > + maxItems: 1 > > + > > +required: > > + - compatible > > + - reg > > + - "#clock-cells" > > + - clocks > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + > > + osc2_clk: osc2-clk { > > + compatible = "fixed-clock"; > > + clock-frequency = <20000000>; > > + #clock-cells = <0>; > > + }; > > + > > + soc { > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + pipllct: clock-controller@24220000 { > > + compatible = "toshiba,tmpv7708-pipllct"; > > The driver makes it look like this is actually part of a syscon node. Is > that right? It's not clear to me that this is a syscon. But then looking > at the binding it seems that one device has been split up into PLL and > "not PLL" parts sort of arbitrarily. This is the driver that controls the PIPLLCT device that produces the PLL. This device only has the ability to generate his PLL, no other features. I have received similar comments in the driver patch from you, so I will check that as well. > > > + reg = <0 0x24220000 0 0x820>; > > + #clock-cells = <1>; > > + clocks = <&osc2_clk>; > > + }; > > + }; > > +... > Best regards, Nobuhiro