This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is ported from downstream Codeaurora v5.4 kernel. The main difference from downstream code is the split of PCIe registers configuration from .init to .post_init, since it requires phy_power_on(). Tested on IPQ6010 based hardware. Changes in v3: * Drop applied patches * Rely on generic code for speed setup * Drop unused macros * Formatting fixes Changes in v2: * Add patch moving GEN3_RELATED macros to a common header * Drop ATU configuration from pcie-qcom * Remove local definition of common registers * Use bulk clk and reset APIs * Remove msi-parent from device-tree Baruch Siach (1): PCI: dwc: tegra: move GEN3_RELATED DBI register to common header Selvam Sathappan Periakaruppan (2): PCI: qcom: add support for IPQ60xx PCIe controller arm64: dts: ipq6018: Add pcie support arch/arm64/boot/dts/qcom/ipq6018.dtsi | 100 +++++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 7 + drivers/pci/controller/dwc/pcie-qcom.c | 141 +++++++++++++++++++ drivers/pci/controller/dwc/pcie-tegra194.c | 6 - 4 files changed, 248 insertions(+), 6 deletions(-) -- 2.33.0
