Quoting Chun-Jie Chen (2021-08-20 04:14:46) > Add MT8195 apmixedsys clock controller which provides Plls > generated from SoC 26m and ssusb clock gate control. > > Signed-off-by: Chun-Jie Chen <chun-jie.chen@xxxxxxxxxxxx> > --- > drivers/clk/mediatek/Kconfig | 8 + > drivers/clk/mediatek/Makefile | 1 + > drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 145 +++++++++++++++++++ > 3 files changed, 154 insertions(+) > create mode 100644 drivers/clk/mediatek/clk-mt8195-apmixedsys.c > > diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig > index 576babd86f98..7ba1f4118e0d 100644 > --- a/drivers/clk/mediatek/Kconfig > +++ b/drivers/clk/mediatek/Kconfig > @@ -580,6 +580,14 @@ config COMMON_CLK_MT8192_VENCSYS > help > This driver supports MediaTek MT8192 vencsys clocks. > > +config COMMON_CLK_MT8195 > + bool "Clock driver for MediaTek MT8195" > + depends on ARM64 || COMPILE_TEST > + select COMMON_CLK_MEDIATEK > + default ARM64 Please no. The default should presumably be ARCH_MEDIATEK, or just nothing at all. > + help > + This driver supports MediaTek MT8195 basic clocks. > + > config COMMON_CLK_MT8516 > bool "Clock driver for MediaTek MT8516" > depends on ARCH_MEDIATEK || COMPILE_TEST
