Can you please Cc folks who have reviewed prior series when you send
again?
Quoting Rajesh Patil (2021-08-26 06:15:25)
> From: Roja Rani Yarubandi <rojay@xxxxxxxxxxxxxx>
>
> Add QSPI DT node and qspi_opp_table for SC7280 SoC.
Might be worth adding here that we put the opp table in / because SPI
nodes assume any child node is a spi device and so we can't put the
table underneath the spi controller.
>
> Signed-off-by: Roja Rani Yarubandi <rojay@xxxxxxxxxxxxxx>
> Signed-off-by: Rajesh Patil <rajpat@xxxxxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 62 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 62 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 53a21d0..f8dd5ff 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -1318,6 +1337,24 @@
> };
> };
>
> + qspi: spi@88dc000 {
> + compatible = "qcom,qspi-v1";
> + reg = <0 0x088dc000 0 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
> + <&gcc GCC_QSPI_CORE_CLK>;
> + clock-names = "iface", "core";
> + interconnects = <&gem_noc MASTER_APPSS_PROC 0
> + &cnoc2 SLAVE_QSPI_0 0>;
> + interconnect-names = "qspi-config";
> + power-domains = <&rpmhpd SC7280_CX>;
> + operating-points-v2 = <&qspi_opp_table>;
> + status = "disabled";
> +
Nitpick: Drop newline above.
> + };
> +
> dc_noc: interconnect@90e0000 {
> reg = <0 0x090e0000 0 0x5080>;
> compatible = "qcom,sc7280-dc-noc";
