On Fri, Aug 20, 2021 at 7:17 PM Chun-Jie Chen <chun-jie.chen@xxxxxxxxxxxx> wrote: > > Add MT8195 clock dt-bindings, include topckgen, apmixedsys, > infracfg_ao, pericfg_ao and subsystem clocks. > > Signed-off-by: Chun-Jie Chen <chun-jie.chen@xxxxxxxxxxxx> > --- > include/dt-bindings/clock/mt8195-clk.h | 864 +++++++++++++++++++++++++ > 1 file changed, 864 insertions(+) > create mode 100644 include/dt-bindings/clock/mt8195-clk.h > > diff --git a/include/dt-bindings/clock/mt8195-clk.h b/include/dt-bindings/clock/mt8195-clk.h > new file mode 100644 > index 000000000000..95cf812a0b37 > --- /dev/null > +++ b/include/dt-bindings/clock/mt8195-clk.h > @@ -0,0 +1,864 @@ [...] > +/* WPESYS_VPP0 */ > + > +#define CLK_WPE_VPP0_VECI 0 > +#define CLK_WPE_VPP0_VEC2I 1 > +#define CLK_WPE_VPP0_VEC3I 2 > +#define CLK_WPE_VPP0_WPEO 3 > +#define CLK_WPE_VPP0_MSKO 4 > +#define CLK_WPE_VPP0_VGEN 5 > +#define CLK_WPE_VPP0_EXT 6 > +#define CLK_WPE_VPP0_VFC 7 > +#define CLK_WPE_VPP0_CACH0_TOP 8 > +#define CLK_WPE_VPP0_CACH0_DMA 9 > +#define CLK_WPE_VPP0_CACH1_TOP 10 > +#define CLK_WPE_VPP0_CACH1_DMA 11 > +#define CLK_WPE_VPP0_CACH2_TOP 12 > +#define CLK_WPE_VPP0_CACH2_DMA 13 > +#define CLK_WPE_VPP0_CACH3_TOP 14 > +#define CLK_WPE_VPP0_CACH3_DMA 15 > +#define CLK_WPE_VPP0_PSP 16 > +#define CLK_WPE_VPP0_PSP2 17 > +#define CLK_WPE_VPP0_SYNC 18 > +#define CLK_WPE_VPP0_C24 19 > +#define CLK_WPE_VPP0_MDP_CROP 20 > +#define CLK_WPE_VPP0_ISP_CROP 21 > +#define CLK_WPE_VPP0_TOP 22 > +#define CLK_WPE_VPP0_NR_CLK 23 > + > +/* WPESYS_VPP1 */ > + > +#define CLK_WPE_VPP1_VECI 0 > +#define CLK_WPE_VPP1_VEC2I 1 > +#define CLK_WPE_VPP1_VEC3I 2 > +#define CLK_WPE_VPP1_WPEO 3 > +#define CLK_WPE_VPP1_MSKO 4 > +#define CLK_WPE_VPP1_VGEN 5 > +#define CLK_WPE_VPP1_EXT 6 > +#define CLK_WPE_VPP1_VFC 7 > +#define CLK_WPE_VPP1_CACH0_TOP 8 > +#define CLK_WPE_VPP1_CACH0_DMA 9 > +#define CLK_WPE_VPP1_CACH1_TOP 10 > +#define CLK_WPE_VPP1_CACH1_DMA 11 > +#define CLK_WPE_VPP1_CACH2_TOP 12 > +#define CLK_WPE_VPP1_CACH2_DMA 13 > +#define CLK_WPE_VPP1_CACH3_TOP 14 > +#define CLK_WPE_VPP1_CACH3_DMA 15 > +#define CLK_WPE_VPP1_PSP 16 > +#define CLK_WPE_VPP1_PSP2 17 > +#define CLK_WPE_VPP1_SYNC 18 > +#define CLK_WPE_VPP1_C24 19 > +#define CLK_WPE_VPP1_MDP_CROP 20 > +#define CLK_WPE_VPP1_ISP_CROP 21 > +#define CLK_WPE_VPP1_TOP 22 > +#define CLK_WPE_VPP1_NR_CLK 23 If WPE_VPP0 and WPE_VPP1 end up being identical hardware, then there's no need to have two separate lists. [...] > +/* VENCSYS */ > + > +#define CLK_VENC_LARB 0 > +#define CLK_VENC_VENC 1 > +#define CLK_VENC_JPGENC 2 > +#define CLK_VENC_JPGDEC 3 > +#define CLK_VENC_JPGDEC_C1 4 > +#define CLK_VENC_GALS 5 > +#define CLK_VENC_NR_CLK 6 > + > +/* VENCSYS_CORE1 */ > + > +#define CLK_VENC_CORE1_LARB 0 > +#define CLK_VENC_CORE1_VENC 1 > +#define CLK_VENC_CORE1_JPGENC 2 > +#define CLK_VENC_CORE1_JPGDEC 3 > +#define CLK_VENC_CORE1_JPGDEC_C1 4 > +#define CLK_VENC_CORE1_GALS 5 > +#define CLK_VENC_CORE1_NR_CLK 6 Same for VENC and VENC_CORE1. ChenYu
