Hi,Ezequiel, Thanks for your reviewing. On Tue, 2021-08-24 at 08:02 -0300, Ezequiel Garcia wrote: > Hi Irui, > > On Mon, 16 Aug 2021 at 08:00, Irui Wang <irui.wang@xxxxxxxxxxxx> > wrote: > > > > Enable MT8195 two H.264 venc cores, updates vcodec binding > > document. > > > > Signed-off-by: Irui Wang <irui.wang@xxxxxxxxxxxx> > > --- > > Documentation/devicetree/bindings/media/mediatek-vcodec.txt | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/media/mediatek- > > vcodec.txt b/Documentation/devicetree/bindings/media/mediatek- > > vcodec.txt > > index de961699ba0a..eb2e24c32426 100644 > > --- a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt > > +++ b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt > > @@ -11,6 +11,8 @@ Required properties: > > "mediatek,mt8173-vcodec-dec" for MT8173 decoder. > > "mediatek,mt8192-vcodec-enc" for MT8192 encoder. > > "mediatek,mt8195-vcodec-enc" for MT8195 encoder. > > + "mediatek,mtk-venc-core0" for MT8195 avc core0 device. > > + "mediatek,mtk-venc-core1" for MT8195 avc core1 device. > > What is the difference between core0 and core1? > > Thanks, > Ezequiel Both core0 and core1 are H264 encoder hardware, they have their own hardware register base, used power-domains/clocks/irqs. We can use any of them for H.264 encoding, but the two cores can work together for higher performance, it's called "frame racing", a hardware encoding mode, control flow just like in the commit messages: core0 frame#0.frame#2.frame#4... core1 frame#1.frame#3.frame#5... Thanks
