On Fri, Aug 20, 2021 at 06:00:21PM +0200, Pali Rohár wrote: > This property specifies slot power limit in mW unit. It is form-factor and > board specific value and must be initialized by hardware. > > Some PCIe controllers delegates this work to software to allow hardware > flexibility and therefore this property basically specifies what should > host bridge programs into PCIe Slot Capabilities registers. > > Property needs to be specified in mW unit, and not in special format > defined by Slot Capabilities (which encodes scaling factor or different > unit). Host drivers should convert value from mW unit to their format. > > Signed-off-by: Pali Rohár <pali@xxxxxxxxxx> > --- > Documentation/devicetree/bindings/pci/pci.txt | 6 ++++++ > 1 file changed, 6 insertions(+) This needs to be in dtschema schemas/pci/pci-bus.yaml instead. (pci.txt is still here because it needs to be relicensed to move all the descriptions to pci-bus.yaml.) > > diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt > index 6a8f2874a24d..e67d5db21514 100644 > --- a/Documentation/devicetree/bindings/pci/pci.txt > +++ b/Documentation/devicetree/bindings/pci/pci.txt > @@ -32,6 +32,12 @@ driver implementation may support the following properties: > root port to downstream device and host bridge drivers can do programming > which depends on CLKREQ signal existence. For example, programming root port > not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal. > +- slot-power-limit: > + If present this property specifies slot power limit in mW unit. Host drivers As mentioned, this should have a unit suffix. I'm not sure it is beneficial to share with SFP in this case though. > + can parse this slot power limit and use it for programming Root Port or host > + bridge, or for composing and sending PCIe Set_Slot_Power_Limit message > + through the Root Port or host bridge when transitioning PCIe link from a > + non-DL_Up Status to a DL_Up Status. I no nothing about how this mechanism works, but I think this belongs in the next section as for PCIe, a slot is always below a PCI-PCI bridge. If we have N slots, then there's N bridges and needs to be N slot-power-limit properties, right? (The same is probably true for all the properties here except linux,pci-domain.) There's no distinction between host and PCI bridges in pci-bus.yaml though. Rob
