On Fri, Aug 20, 2021 at 7:20 PM Chun-Jie Chen
<chun-jie.chen@xxxxxxxxxxxx> wrote:
>
> Add MT8195 apmixedsys clock controller which provides Plls
> generated from SoC 26m and ssusb clock gate control.
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@xxxxxxxxxxxx>
> ---
> drivers/clk/mediatek/Kconfig | 8 +
> drivers/clk/mediatek/Makefile | 1 +
> drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 145 +++++++++++++++++++
> 3 files changed, 154 insertions(+)
> create mode 100644 drivers/clk/mediatek/clk-mt8195-apmixedsys.c
>
> diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> index 576babd86f98..7ba1f4118e0d 100644
> --- a/drivers/clk/mediatek/Kconfig
> +++ b/drivers/clk/mediatek/Kconfig
> @@ -580,6 +580,14 @@ config COMMON_CLK_MT8192_VENCSYS
> help
> This driver supports MediaTek MT8192 vencsys clocks.
>
> +config COMMON_CLK_MT8195
> + bool "Clock driver for MediaTek MT8195"
> + depends on ARM64 || COMPILE_TEST
> + select COMMON_CLK_MEDIATEK
> + default ARM64
> + help
> + This driver supports MediaTek MT8195 basic clocks.
Since we will have all clocks under the same Kconfig option, please
drop the word "basic".
> +
> config COMMON_CLK_MT8516
> bool "Clock driver for MediaTek MT8516"
> depends on ARCH_MEDIATEK || COMPILE_TEST
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 15bc045f0b71..d4157cfca865 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -80,5 +80,6 @@ obj-$(CONFIG_COMMON_CLK_MT8192_MSDC) += clk-mt8192-msdc.o
> obj-$(CONFIG_COMMON_CLK_MT8192_SCP_ADSP) += clk-mt8192-scp_adsp.o
> obj-$(CONFIG_COMMON_CLK_MT8192_VDECSYS) += clk-mt8192-vdec.o
> obj-$(CONFIG_COMMON_CLK_MT8192_VENCSYS) += clk-mt8192-venc.o
> +obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195-apmixedsys.o
> obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
> obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
> diff --git a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
> new file mode 100644
> index 000000000000..253eb30b22d4
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c
> @@ -0,0 +1,145 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +//
> +// Copyright (c) 2021 MediaTek Inc.
> +// Author: Chun-Jie Chen <chun-jie.chen@xxxxxxxxxxxx>
> +
> +#include "clk-gate.h"
> +#include "clk-mtk.h"
> +
> +#include <dt-bindings/clock/mt8195-clk.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +
> +static const struct mtk_gate_regs apmixed_cg_regs = {
> + .set_ofs = 0x8,
> + .clr_ofs = 0x8,
> + .sta_ofs = 0x8,
> +};
> +
> +#define GATE_APMIXED(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
> +
> +static const struct mtk_gate apmixed_clks[] = {
> + GATE_APMIXED(CLK_APMIXED_PLL_SSUSB26M, "pll_ssusb26m", "clk26m", 1),
> +};
> +
> +#define MT8195_PLL_FMAX (3800UL * MHZ)
> +#define MT8195_PLL_FMIN (1500UL * MHZ)
> +#define MT8195_INTEGER_BITS 8
> +
> +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
> + _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \
> + _tuner_reg, _tuner_en_reg, _tuner_en_bit, \
> + _pcw_reg, _pcw_shift, _pcw_chg_reg, \
> + _en_reg, _pll_en_bit) { \
Nit: Even for macro definitions, you could align the lines to the opening
parenthesis. That would give you more room. And it would make it slightly
easier to read.
Otherwise,
Reviewed-by: Chen-Yu Tsai <wenst@xxxxxxxxxxxx>
[...]
