Hi, On Fri, Aug 20, 2021 at 7:17 PM Chun-Jie Chen <chun-jie.chen@xxxxxxxxxxxx> wrote: > > This patch adds the new binding documentation for system clock > and functional clock on Mediatek MT8195. > > Signed-off-by: Chun-Jie Chen <chun-jie.chen@xxxxxxxxxxxx> > --- > .../arm/mediatek/mediatek,mt8195-clock.yaml | 254 ++++++++++++++++++ > .../mediatek/mediatek,mt8195-sys-clock.yaml | 73 +++++ > 2 files changed, 327 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml > > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml > new file mode 100644 > index 000000000000..17fcbb45d121 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-clock.yaml > @@ -0,0 +1,254 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-clock.yaml#"; > +$schema: "http://devicetree.org/meta-schemas/core.yaml#"; > + > +title: MediaTek Functional Clock Controller for MT8195 > + > +maintainers: > + - Chun-Jie Chen <chun-jie.chen@xxxxxxxxxxxx> > + > +description: > + The clock architecture in Mediatek like below > + PLLs --> > + dividers --> > + muxes > + --> > + clock gate > + > + The devices except apusys_pll provide clock gate control in different IP blocks. > + The apusys_pll provides Plls which generated from SoC 26m for AI Processing Unit. > + > +properties: > + compatible: > + items: > + - enum: > + - mediatek,mt8195-scp_adsp > + - mediatek,mt8195-imp_iic_wrap_s > + - mediatek,mt8195-imp_iic_wrap_w > + - mediatek,mt8195-mfgcfg > + - mediatek,mt8195-vppsys0 > + - mediatek,mt8195-wpesys > + - mediatek,mt8195-wpesys_vpp0 > + - mediatek,mt8195-wpesys_vpp1 > + - mediatek,mt8195-vppsys1 > + - mediatek,mt8195-imgsys > + - mediatek,mt8195-imgsys1_dip_top > + - mediatek,mt8195-imgsys1_dip_nr > + - mediatek,mt8195-imgsys1_wpe > + - mediatek,mt8195-ipesys > + - mediatek,mt8195-camsys > + - mediatek,mt8195-camsys_rawa > + - mediatek,mt8195-camsys_yuva > + - mediatek,mt8195-camsys_rawb > + - mediatek,mt8195-camsys_yuvb > + - mediatek,mt8195-camsys_mraw > + - mediatek,mt8195-ccusys > + - mediatek,mt8195-vdecsys_soc > + - mediatek,mt8195-vdecsys > + - mediatek,mt8195-vdecsys_core1 > + - mediatek,mt8195-vencsys > + - mediatek,mt8195-vencsys_core1 > + - mediatek,mt8195-apusys_pll The indentation is slightly off by 2 extra spaces. [...] > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml > new file mode 100644 > index 000000000000..dbf33ea6cb9f > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml > @@ -0,0 +1,73 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-sys-clock.yaml#"; > +$schema: "http://devicetree.org/meta-schemas/core.yaml#"; > + > +title: MediaTek System Clock Controller for MT8195 > + > +maintainers: > + - Chun-Jie Chen <chun-jie.chen@xxxxxxxxxxxx> > + > +description: > + The clock architecture in Mediaek like below Typo. > + PLLs --> > + dividers --> > + muxes > + --> > + clock gate > + > + The apmixedsys provides most of PLLs which generated from SoC 26m. > + The topckgen provides dividers and muxes which provide the clock source to other IP blocks. > + The infracfg_ao and pericfg_ao provides clock gate in peripheral and infrastructure IP blocks. > + > +properties: > + compatible: > + items: > + - enum: > + - mediatek,mt8195-topckgen > + - mediatek,mt8195-infracfg_ao > + - mediatek,mt8195-apmixedsys > + - mediatek,mt8195-pericfg_ao Indentation off here as well. Otherwise, Reviewed-by: Chen-Yu Tsai <wenst@xxxxxxxxxxxx>
