On Wed, 2021-08-18 at 09:20 -0500, Rob Herring wrote: > On Wed, Aug 11, 2021 at 3:02 AM Chunfeng Yun (云春峰) > <Chunfeng.Yun@xxxxxxxxxxxx> wrote: > > > > On Fri, 2021-08-06 at 14:43 -0600, Rob Herring wrote: > > > On Fri, Jul 30, 2021 at 04:49:54PM +0800, Chunfeng Yun wrote: > > > > There are 4 USB controllers on MT8195, the controllers > > > > (IP1~IP3, > > > > exclude IP0) have a wrong default SOF/ITP interval which is > > > > calculated from the frame counter clock 24Mhz by default, but > > > > in fact, the frame counter clock is 48Mhz, so we should set > > > > the accurate interval according to 48Mhz. Here add a new > > > > compatible > > > > for MT8195, it's also supported in driver. But the first > > > > controller > > > > (IP0) has no such issue, we prefer to use generic compatible, > > > > e.g. mt8192's compatible. > > > > > > That only works until you find some 8195 bug common to all > > > instances. > > > > It's also OK for IP0 to use mt8195's compatible, these setting > > value is > > the same as IP0's default value, use mt8192's may avoid these dummy > > setting. > > I still don't understand. By use mt8192's compatible, that means you > have for IP0: > > compatible = "mediatek,mt8192-xhci", "mediatek,mtk-xhci"; > > And for the rest: > compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci"; No, use "mediatek,mt8195-xhci" is also ok for IP0. Seems need modify commit log and remove last sentence to avoid misunderstanding. Thanks > > If there's a 8195 quirk you need to work around, then you can't on > IP0. You need to be able to address quirks in the future without > changing the DTB. That is why we require SoC specific compatibles > even > when IP blocks are 'the same'. > > Rob
