On Tue, Aug 17, 2021 at 12:50:22PM +0200, Jan Lübbe wrote: > On Tue, 2021-08-17 at 11:38 +0200, Krzysztof Kozlowski wrote: > > Include dt-bindings for Marvell Armada XP SDRAM and L2 cache ECC in the > > EDAC-ARMADA entry. > > The L2 cache binding is already described in > Documentation/devicetree/bindings/arm/l2c2x0.yaml, so this is only for the > SDRAM. Fixed up and applied. Rob
