On Tue, Aug 10, 2021 at 11:31:42AM +0200, Krzysztof Kozlowski wrote:
> Merge Exynos4210 and Exynos4412 clock controller bindings to existing DT
> schema.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxxxxx>
> ---
> .../bindings/clock/exynos4-clock.txt | 86 -------------------
> .../bindings/clock/samsung,exynos-clock.yaml | 29 ++++++-
> 2 files changed, 28 insertions(+), 87 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/exynos4-clock.txt
>
> diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
> deleted file mode 100644
> index 17bb11365354..000000000000
> --- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
> +++ /dev/null
> @@ -1,86 +0,0 @@
> -* Samsung Exynos4 Clock Controller
> -
> -The Exynos4 clock controller generates and supplies clock to various controllers
> -within the Exynos4 SoC. The clock binding described here is applicable to all
> -SoC's in the Exynos4 family.
> -
> -Required Properties:
> -
> -- compatible: should be one of the following.
> - - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
> - - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.
> -
> -- reg: physical base address of the controller and length of memory mapped
> - region.
> -
> -- #clock-cells: should be 1.
> -
> -Each clock is assigned an identifier and client nodes can use this identifier
> -to specify the clock which they consume.
> -
> -All available clocks are defined as preprocessor macros in
> -dt-bindings/clock/exynos4.h header and can be used in device
> -tree sources.
> -
> -Example 1: An example of a clock controller node is listed below.
> -
> - clock: clock-controller@10030000 {
> - compatible = "samsung,exynos4210-clock";
> - reg = <0x10030000 0x20000>;
> - #clock-cells = <1>;
> - };
> -
> -Example 2: UART controller node that consumes the clock generated by the clock
> - controller. Refer to the standard clock bindings for information
> - about 'clocks' and 'clock-names' property.
> -
> - serial@13820000 {
> - compatible = "samsung,exynos4210-uart";
> - reg = <0x13820000 0x100>;
> - interrupts = <0 54 0>;
> - clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
> - clock-names = "uart", "clk_uart_baud0";
> - };
> -
> -Exynos4412 SoC contains some additional clocks for FIMC-ISP (Camera ISP)
> -subsystem. Registers for those clocks are located in the ISP power domain.
> -Because those registers are also located in a different memory region than
> -the main clock controller, a separate clock controller has to be defined for
> -handling them.
> -
> -Required Properties:
> -
> -- compatible: should be "samsung,exynos4412-isp-clock".
> -
> -- reg: physical base address of the ISP clock controller and length of memory
> - mapped region.
> -
> -- #clock-cells: should be 1.
> -
> -- clocks: list of the clock controller input clock identifiers,
> - from common clock bindings, should point to CLK_ACLK200 and
> - CLK_ACLK400_MCUISP clocks from the main clock controller.
> -
> -- clock-names: list of the clock controller input clock names,
> - as described in clock-bindings.txt, should be "aclk200" and
> - "aclk400_mcuisp".
> -
> -- power-domains: a phandle to ISP power domain node as described by
> - generic PM domain bindings.
> -
> -Example 3: The clock controllers bindings for Exynos4412 SoCs.
> -
> - clock: clock-controller@10030000 {
> - compatible = "samsung,exynos4412-clock";
> - reg = <0x10030000 0x18000>;
> - #clock-cells = <1>;
> - };
> -
> - isp_clock: clock-controller@10048000 {
> - compatible = "samsung,exynos4412-isp-clock";
> - reg = <0x10048000 0x1000>;
> - #clock-cells = <1>;
> - power-domains = <&pd_isp>;
> - clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>;
> - clock-names = "aclk200", "aclk400_mcuisp";
> - };
> diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
> index c7b07fcd3fa1..ea73201f259b 100644
> --- a/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
> +++ b/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
> @@ -23,6 +23,9 @@ properties:
> - samsung,exynos3250-cmu
> - samsung,exynos3250-cmu-dmc
> - samsung,exynos3250-cmu-isp
> + - samsung,exynos4210-clock
> + - samsung,exynos4412-clock
> + - samsung,exynos4412-isp-clock
> - samsung,exynos5250-clock
> - samsung,exynos5420-clock
> - samsung,exynos5800-clock
> @@ -35,11 +38,18 @@ properties:
> assigned-clocks: true
> assigned-clock-parents: true
> assigned-clock-rates: true
> - clocks: true
> + clocks:
> + description: |
> + For samsung,exynos4412-isp-clock, the input clocks should be CLK_ACLK200
> + and CLK_ACLK400_MCUISP from the main clock controller.
> +
> + clock-names: true
>
> "#clock-cells":
> const: 1
>
> + power-domains: true
> +
How many?
Now all the flavors can have a power domain? Maybe this should be a
separate binding given this and the if/then below.
> reg:
> maxItems: 1
>
> @@ -50,6 +60,23 @@ required:
>
> additionalProperties: false
>
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: samsung,exynos4412-isp-clock
> + then:
> + properties:
> + clock-names:
> + items:
> + - const: aclk200
> + - const: aclk400_mcuisp
> + required:
> + - clocks
> + - clock-names
> + - power-domains
> +
> examples:
> - |
> #include <dt-bindings/clock/exynos5250.h>
> --
> 2.30.2
>
>
