> > > +static int apple_pcie_setup_refclk(void __iomem *rc,
> > > + void __iomem *port,
> > > + unsigned int idx)
> > > +{
> > > + u32 stat;
> > > + int res;
> > > +
> > > + res = readl_poll_timeout(rc + CORE_RC_PHYIF_STAT, stat,
> > > + stat & CORE_RC_PHYIF_STAT_REFCLK, 100, 50000);
> > > + if (res < 0)
> > > + return res;
> > > +
> > > + rmwl(0, CORE_LANE_CTL_CFGACC, rc + CORE_LANE_CTL(idx));
> > > + rmwl(0, CORE_LANE_CFG_REFCLK0REQ, rc + CORE_LANE_CFG(idx));
> > > +
> > > + res = readl_poll_timeout(rc + CORE_LANE_CFG(idx), stat,
> > > + stat & CORE_LANE_CFG_REFCLK0ACK, 100, 50000);
> > > + if (res < 0)
> > > + return res;
> > > +
> > > + rmwl(0, CORE_LANE_CFG_REFCLK1, rc + CORE_LANE_CFG(idx));
> > > + res = readl_poll_timeout(rc + CORE_LANE_CFG(idx), stat,
> > > + stat & CORE_LANE_CFG_REFCLK1, 100, 50000);
> > > +
> > > + if (res < 0)
> > > + return res;
> > > +
> > > + rmwl(CORE_LANE_CTL_CFGACC, 0, rc + CORE_LANE_CTL(idx));
> > > + udelay(1);
> > > + rmwl(0, CORE_LANE_CFG_REFCLKEN, rc + CORE_LANE_CFG(idx));
> > > +
> > > + rmwl(0, PORT_REFCLK_EN, port + PORT_REFCLK);
> > > +
> > > + return 0;
> > > +}
>
> This really wants to be moved to its own clock driver, unless there is
> a strong guarantee that the clock tree isn't shared with anything
> else. I expect that parts of that clock tree will need to be
> refcounted, and that's where having a real clock driver will help.
>
> I also have the strong feeling that the clock hierarchy will need to
> be described in DT one way or another, if only to be able to cope with
> future revisions of this block.
Could be, but this is the most magical part of the driver (no docs...)
and that means it's prohibitively difficult to design useful DT
bindings...
For whatever it's worth the Corellium code doesn't expose any DT
bindings here, so maybe this hasn't changed since older Apple SoCs.
Orthogonal to this magic code, we /do/ need DT bindings for the
clock/power gates. At the moment, m1n1 enables the PCIe clock and leaves
it on, so it's not urgent for this series. But in the future when we
want fine grained power management, we'll need it modeled. Sven has a
WIP clock gate driver and proposed bindings, which can be added to the
PCIe DT later nonintrusively. That shouldn't block this series, however.
